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47 Commits

Author SHA1 Message Date
aolofsson
289024fd89 Flattening directory tree (again) 
- Creating an arbitrary 'src' directory really doesn't help much...
- Goal is to make each folder self contained
- Make meta repos and individual repos have the same directory structure
 2022-06-21 14:48:48 -04:00
aolofsson
e89f815b38 Going back to placing all folders in src 
- Only way to scale, final decision!!
 2022-05-29 08:45:00 -04:00
Andreas.Olofsson
d6f5de24d7 Changing hierarchy to promote blocks 2020-01-28 18:12:57 -05:00
Andreas Olofsson
7094173ae9 Reorg! Why? 
- The top level directory was not scaling, too imposing
- Friendlier to download a repo and see a finite number of top level dirs
- We are just getting started...
 2016-03-22 08:13:40 -04:00
Andreas Olofsson
f60f3515e6 Making front page table links to README files 
-Every folder should be more or less self contained
-Hopefully one day this repo will look more like parallella-examples
 2016-03-10 07:38:06 -05:00
Andreas Olofsson
d9f18e7b58 DV cleanup 
-removing all redundant build files, there must be only one...
 2016-03-08 21:23:02 -05:00
Andreas Olofsson
a5194a30a3 Reorg 
-Renaming constants files as ".vh"
-Cleanup parameters
 2016-02-26 19:08:40 -05:00
Andreas Olofsson
0327ca1df3 Merge branch 'master' of https://github.com/parallella/oh 2016-01-20 21:48:06 -05:00
Andreas Olofsson
5b15aa2b79 Adding IP packaging files 2016-01-20 17:36:57 -05:00
Ola Jeppsson
cf4aa62027 Fix mailbox interrupt 
Use IRQ_F2P for interrupts, this is what other designs seem to do.
Use interrupt pin 11 (maps to IRQ=87 devicetree-IRQ=55 (87-32)).

Disable CORE0_FIQ_INTR as we no longer use it.

Add concat ip, apparently needed:
http://www.xilinx.com/support/answers/58942.html

Add constant_zero, and constant_one outputs to parallella_base module.

Tie all unused (by PL) interrupts on the F2P port to 0.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-01-20 22:30:56 +01:00
Andreas Olofsson
e86567241d Cleanup 2016-01-19 16:06:38 -05:00
Andreas Olofsson
32522280e6 Cleanup 2016-01-10 15:58:28 -05:00
Andreas Olofsson
f5bb42dfe3 Moving axi cells to own folder 2015-12-04 03:38:26 -05:00
Andreas Olofsson
7b8460b145 Fixing up issues with database reorg 
- Not sure where the prog_full issue popped up from. (sign of disorganized databsae)
-
 2015-11-30 15:07:28 -05:00
Andreas Olofsson
19fa611bb9 Massive reorganization to impove reuse 
- adding more chip code
- pushing memory stuff into common
- making common "oh_" naming class
-
 2015-11-30 13:45:49 -05:00
Andreas Olofsson
b58ceef19c Merge branch 'master' of https://github.com/parallella/oh 2015-11-29 12:42:24 -05:00
Andreas Olofsson
9ddd71024d Fixing system_bd interface for "mailbox_irq" signal 2015-11-29 12:41:53 -05:00
Peter Saunderson
889b24d72e Added Makefiles to make build easier 
Signed-off-by: Peter Saunderson <peteasa@gmail.com>
 2015-11-29 14:44:21 +00:00
Andreas Olofsson
a44778b8be Putting all ip generator blocks in one repo 2015-11-13 16:21:53 -05:00
Andreas Olofsson
24afa3c9a0 Deleting old files 2015-11-12 11:00:23 -05:00
Andreas Olofsson
3f1296b099 Cleanup 2015-11-12 10:50:05 -05:00
Andreas Olofsson
9ada08a42c Adding parallella.bit.bin 2015-11-11 14:28:38 -05:00
Andreas Olofsson
038d39def7 Defparam typo 
- Not caught by iverilog!! (file bug??)
- Caught by Vivado.
 2015-11-11 14:13:38 -05:00
Andreas Olofsson
0a2ea66b7e Bug fix. Adding missing ID parameter. 
- would only show up at different ID
- better to always make defauly nonsense
- sneaky...
 2015-11-11 13:58:04 -05:00
Andreas Olofsson
3f0efb9db2 Adding dummy.elf for bootgen 2015-11-11 13:56:48 -05:00
Andreas Olofsson
464700c0b9 Adding converter script for bootgen 2015-11-11 13:56:09 -05:00
Andreas Olofsson
bb084f1670 Adding skeleton for adi sdr design 
Now need to integrate elink in this
 2015-11-11 00:42:14 -05:00
Andreas Olofsson
62305244e9 Build script fixup + gitignore 
- Filtering "src" wasn't such a good idea...
- Fixing script for bitstream, bootgen doesn't overwrite existing bit stream files (thanks Xilinx, cost me an hour of anxiety!!)
 2015-11-11 00:29:15 -05:00
Andreas Olofsson
61eb56c6f7 Final Vivado fixups: 
- reduced frame fanout, removed clock gater in erx_io (improves speed path)
- driving constants on "wid signals" (proper)
- making lock signal 1 bit wide to remove warning
- moved backed to BUFIO for IDDR blocks
 2015-11-09 16:09:12 -05:00
Andreas Olofsson
c84e1c96b7 Adding hdmi pins for parallella 2015-11-09 13:22:08 -05:00
Andreas Olofsson
01fd24e069 Fixing synchronization reset speed path 
- This seems silly, why even have a syncrhonizer
- Safe to set speed path?
 2015-11-09 00:16:35 -05:00
Andreas Olofsson
405c322d75 Adding build shell script for headless 2015-11-08 07:33:16 -05:00
Andreas Olofsson
9383f32764 Making sure ETYPE is set to 0. 2015-11-06 22:41:43 -05:00
Andreas Olofsson
aa940c2a39 Fixing typos 2015-11-06 22:40:59 -05:00
Andreas Olofsson
8b3fa77df1 Added missing index 2015-11-06 20:47:16 -05:00
Andreas Olofsson
1fa3543ba1 Changing back to lower cases, works.. 2015-11-06 20:46:41 -05:00
Andreas Olofsson
6e2ee17481 Updated system memory map 2015-11-06 20:44:18 -05:00
Andreas Olofsson
c9dc9c33ee Almost done connecting 
- AXI connections not working properly...
 2015-11-06 18:26:09 -05:00
Andreas Olofsson
63bf5d25a4 Moving to active low reset 
- Because this is the right thing to do for chips
- Not going to tell you why...
 2015-11-06 16:51:57 -05:00
Andreas Olofsson
8a89b7e185 Adding more structured vivado build files 2015-11-06 14:11:46 -05:00
Andreas Olofsson
84b5af5b3a Cleanup 2015-11-06 14:10:35 -05:00
Andreas Olofsson
3969e6d19e Moving to MIT license 2015-11-06 11:25:05 -05:00
Andreas Olofsson
8b2974feae Massive reorg! 
- flattening hierarchy
- removing junk
 2015-11-06 10:59:22 -05:00
Andreas Olofsson
0fcea92b0d Scripts per "project" 2015-11-06 06:58:47 -05:00
Andreas Olofsson
90998b8ad0 Adding parallella synthesis scripts 2015-11-06 06:58:14 -05:00
Andreas Olofsson
6cb5f88073 Moving block deisgns into a single Parallella module 
- Easier to maintain
- Better sandbox
 2015-11-06 06:56:56 -05:00
Andreas Olofsson
bc53400888 Adding parallella block design 
-Start with gui
-Generate block design
-Edit text, this is f'ing crazy!
-If this is the only way to use the vivado IP not sure I want it
-Strive towards doing everything in verilog
-Split into:
1.) Verilog block (no IP!)
2.) One top level to instantiate IP + clean verilog block
-Never fight the tools..
 2015-05-22 21:38:39 -04:00