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Author SHA1 Message Date
Andreas.Olofsson
3c8da0f727 One line compile script 2020-03-05 09:02:00 -05:00
Andreas.Olofsson
419d9a67ad Adding simple profile script for spike 
-meant to be used with excel
 2020-03-05 09:01:19 -05:00
Andreas.Olofsson
a09374d74b Adding FAIL timeout condition in test 2020-02-15 21:58:17 -05:00
Andreas.Olofsson
82f160561e Only write result for r0-31 
-Add spcial csrs later
 2020-02-15 21:57:11 -05:00
Andreas.Olofsson
0086fa1012 Adding register look up table 
-simulator trace uses abi names, hardware uses raw registers
 2020-02-14 23:28:32 -05:00
Andreas.Olofsson
3fba513a29 Adding script for converting difference trace formats to epiphany 
Speeds up debugging immensly
Goal is to mmake it so that files can be tkdiffed and readable without any extra python scripts to post process
 2020-02-14 21:24:06 -05:00
Andreas.Olofsson
2f2ea2ad93 Fixing bug in address mapping 
-NEeded to divide by width/8
 2020-02-14 21:23:26 -05:00
Andreas.Olofsson
099b9527e3 Customizing linker file per architecture 2020-02-14 21:22:18 -05:00
Andreas.Olofsson
6b01f16935 Addubg asm2elf and elf2hex scripts 2020-02-06 22:11:00 -05:00
Andreas.Olofsson
c04523503e Making stimulus configurable 
-ability to turn off timesetamps dynamically
-ability to ignore valid signal
 2020-02-06 12:50:34 -05:00
Andreas.Olofsson
927b31a811 Improving script comments 2020-02-06 10:05:55 -05:00
Andreas.Olofsson
9e9d323025 Changing the CFG_ASIC approach 
-Should be ifdef, since this is a global. You will never be doing and not an asic at the same time!
 2020-02-04 23:04:52 -05:00
Andreas.Olofsson
21349445ef Change macro name to reduce confusion 2020-02-04 22:43:18 -05:00
Andreas.Olofsson
ca3c01144f Changing stimulus order to avoid on memh 2020-02-04 22:42:41 -05:00
Andreas.Olofsson
e04d6a0615 Adding print to file fuctionality 2020-02-04 20:36:00 -05:00
Andreas.Olofsson
9bb84ebe20 Adding hex2hex file in python 
-Script working!
-Still need to finish the emf format
-Still need to finish proper script commands
 2020-02-04 20:10:09 -05:00
Andreas.Olofsson
f7012f8369 Basic memh based stimulus file. 
-Much cleaner than previous work!
-Allows for loading into FPGA!
 2020-02-03 13:19:55 -05:00
Andreas.Olofsson
1bd7c552fb Adding basic tesbench for stimulus function 
-testing the tester
 2020-02-03 13:19:21 -05:00
Andreas.Olofsson
b23a63e2ba Adding firmware example for readmemh 2020-02-03 13:16:37 -05:00
Andreas.Olofsson
b057d47d57 Duh, fixing CFG_ASIC issue! 
-It's a global, use ifdef to avoid compilation issues
-No need for generate
 2020-02-02 23:12:19 -05:00
Andreas.Olofsson
e017f0f290 Stimulus write port written 
-Read port half done, looks straight forward
 2020-02-02 23:11:29 -05:00
Andreas.Olofsson
c23862f4a6 Starting general purpose design of stimulus! 
-memory based, generic
 2020-02-02 21:35:15 -05:00
Andreas.Olofsson
2c9fd39c87 Adding python package setup scripts 
-Work in progress, learning
 2020-02-01 09:43:37 -05:00
Andreas.Olofsson
7bd980fca2 Adding include directorys to lib.cmd 2020-02-01 09:07:47 -05:00
Andreas.Olofsson
4d8d7e4855 Cleanup of risc-v 2020-01-28 18:34:35 -05:00
Andreas.Olofsson
df50421c5c Cleaing up OH repo 2020-01-28 18:21:52 -05:00
Andreas.Olofsson
d6f5de24d7 Changing hierarchy to promote blocks 2020-01-28 18:12:57 -05:00
Andreas.Olofsson
036926fda4 Adding openroad repo to README 2020-01-28 18:04:19 -05:00
Andreas Olofsson
998f3021cc Fixed elink platform compile errors 
-Ultrascale changes broke the zynq design
-Adding CFG_PLATFORM variable to control compilation target
v1.0 		2017-11-22 11:32:20 -05:00
Andreas Olofsson
8cc0809580 Merge pull request #102 from wasserfuhr/patch-4 
fixed typos
 2017-05-09 06:38:11 -04:00
RaWa
9c614cdfcb fixed typos 2017-04-25 15:24:23 +02:00
Andreas Olofsson
13ff7c7091 Merge pull request #93 from rnestler/glossary_fix 
docs: Fix GPIO description
 2017-04-24 21:59:31 -04:00
Andreas Olofsson
08c9b61d7d Merge pull request #97 from MattPD/patch-1 
oh_add: Fix typo in the function description
 2017-04-24 21:59:11 -04:00
Andreas Olofsson
b26b9188a3 Merge pull request #94 from wasserfuhr/patch-3 
fixed sort order
 2017-04-24 21:58:49 -04:00
Andreas Olofsson
70a6f14794 Merge pull request #99 from olajep/zcu102 
Zcu102
 2017-04-24 21:57:56 -04:00
Andreas Olofsson
b1946a7c94 Changed license copyright 
The Parallella Foundation was resolved. Too much of a headache to maintain.  Considering a permanent home in an existing foundation like eclipse, or apache, or other? For now assigning to me. History of code copyright: Adapteva-->Parallella Foundation-->Andreas Olofsson

1.) Most of code developed while Andreas Olofsson was employed at Adapteva

2.) 2016: Adapteva board resolution transfered code to Parallella Foundation under leadership of Andreas Olofsson

3.) 2016: Parallella foundation resolved and code copyright transferred to Andreas Olofsson

None of this should matter given the MIT nature of the license....
 2017-04-01 17:50:04 -04:00
Ola Jeppsson
2f91330d0f common/fpga/create_ip.tcl: Fix error when sub-IP is locked 
- Make local temporary copy
- Don't fail if IP is locked (can happen when partname has changed)

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-10 17:00:55 +01:00
Ola Jeppsson
37a38ab486 zcu102: zcu102: Use Petalinux 2016.4 design as base 
Change partname to:
xczu9eg-ffvb1156-1-i-es2

Don't set BOARD_PART.

Remove si570 pl component.

Full path:
petalinux-bsp/xilinx-zcu102-zu9-es2-rev1.0-2016.4/hardware/xilinx-zcu102-zu9-es2-rev1.0-2016.4/

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-09 23:03:51 +01:00
Ola Jeppsson
02955c09a5 zcu102: zcu102: Define oh_verilog_define 
Define oh_verilog_define to CFG_ASIC=0.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 23:02:10 +01:00
Ola Jeppsson
fbfe55961c fpga/system_build.tcl: Support oh_verilog_define flag 
Workaround for that recent Vivado versions (2016.4) doesn't seem to
support this any longer:
set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value $foo -objects [get_runs synth_1]

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 23:01:50 +01:00
Ola Jeppsson
ee2e234dae Revert "common/hdl: Fix syntax error when CFG_ASIC is undefined" 
This reverts commit 049a031e47ff2dde7bd12b151649350d56fc2e09.
 2017-02-07 19:11:05 +01:00
Ola Jeppsson
afccd4a38b zcu102: zcu102: Fix Makefile deps and clean target 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 18:47:42 +01:00
Ola Jeppsson
8706590599 zcu102: zcu102: Remove cclk1 port 
Fails implementation since it's unconnected but its IO standard is LVDS.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 18:45:52 +01:00
Ola Jeppsson
258cda93d2 fpga/system_build.tcl: Create files for SDK 
Create files needed by Xilinx SDK tool for FSBL generation.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 18:44:04 +01:00
Ola Jeppsson
23c2f8b383 fpga/system_build.tcl: Tweak implementation optimization settings 
This is what ADI HDL uses. I trust that they know what they're doing.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 18:42:20 +01:00
Ola Jeppsson
f7e8ddfe7d fpga/system_build.tcl: Write raw BIN bitstream file 
Write raw BIN bitstream file without metadata, as well as BIT file.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 18:40:01 +01:00
Ola Jeppsson
66d9a97bda fpga/system_build.tcl: Generate timing summaries 
Generate timing summaries for synthesis and implementation.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 18:37:09 +01:00
Ola Jeppsson
b179a70b27 fpga/system_build.tcl: Use $design instead of hardcoded 'system' 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 17:38:41 +01:00
Ola Jeppsson
82cab68bc4 zcu102: zcu102_base: Fix Makefile dependencies and clean target 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-06 19:45:01 +01:00
Ola Jeppsson
a73f0ae10c zcu102: Synthesize & create bitstream in FPGA project 
Uncomment line.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 21:17:11 +01:00