Andreas Olofsson
3f1296b099
Cleanup
2015-11-12 10:50:05 -05:00
Andreas Olofsson
8820c8500a
Adding wait circuit for axi/elink
2015-11-12 10:47:52 -05:00
Andreas Olofsson
3b2968f162
Clean up test files
2015-11-12 10:46:52 -05:00
Andreas Olofsson
60bdda4dfa
Dead simple test
2015-11-12 00:59:21 -05:00
Andreas Olofsson
a9e034bef9
Bringing access low during wait
2015-11-12 00:58:06 -05:00
Andreas Olofsson
07dff85090
Changing build script to work with xilinx model
2015-11-12 00:56:02 -05:00
Andreas Olofsson
4a7b0d8f1c
Adding proper test or bursting
...
- Need to at a minimum try to fill the fios
- Need to add a wait circuit at the back end of fifo to test pipe
2015-11-11 22:28:53 -05:00
Andreas Olofsson
867b750c50
Adding write from stimulus to dv link1
...
- also, more cleanup of ID parameters
2015-11-11 14:02:02 -05:00
Andreas Olofsson
4885c3f7d2
Adding byte/halfword test
2015-11-11 13:58:55 -05:00
Andreas Olofsson
9c1fb038a9
Adding test for remapping logic
2015-11-11 13:57:18 -05:00
Andreas Olofsson
b2926fdc5e
Adding test for setting east link to half speed
2015-11-10 22:30:41 -05:00
Andreas Olofsson
04cd179f5a
Lint fixes for icarus/verilator
2015-11-09 21:57:25 -05:00
Andreas Olofsson
ef204a875b
Fixed register read/write test
...
- Has been tested with dv_axi to work
2015-11-09 20:39:57 -05:00
Andreas Olofsson
02ae7cf83d
Cleanup
2015-11-09 20:39:48 -05:00
Andreas Olofsson
6dcd5e96bf
Cleanup after lock width change for zynq axi
2015-11-09 20:39:16 -05:00
Andreas Olofsson
13d29f8e67
Stupid typos..
2015-11-09 16:18:20 -05:00
Andreas Olofsson
55ba8ff635
Cleaning up warnings from FGPA tools
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- removing unconnected ports
- only one rst input for async_fifo
- synchronizing the reset input toe emaxi fifo
2015-11-09 13:23:40 -05:00
Andreas Olofsson
01fd24e069
Fixing synchronization reset speed path
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- This seems silly, why even have a syncrhonizer
- Safe to set speed path?
2015-11-09 00:16:35 -05:00
Andreas Olofsson
63bf5d25a4
Moving to active low reset
...
- Because this is the right thing to do for chips
- Not going to tell you why...
2015-11-06 16:51:57 -05:00
Andreas Olofsson
3969e6d19e
Moving to MIT license
2015-11-06 11:25:05 -05:00
Andreas Olofsson
92272e211d
Adding missind dirs in comamnd file
2015-11-04 20:04:44 -05:00
Andreas Olofsson
6b83cdb0d7
Testbench bug fix
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- can't connect a 64 bit interface to a 32bit one...
- (abuse of emaxi..)
2015-11-03 21:50:26 -05:00
Andreas Olofsson
f849f2410f
Adding infrastructure for axi_elink
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- Need to clean up some of these files later
2015-11-03 19:52:08 -05:00
Andreas Olofsson
275ed5252f
Adding test for sweeping idelay and testing reads
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-It works!!!!
2015-11-03 10:30:20 -05:00
Andreas Olofsson
02b22a36f3
Fixing test to conform to new stimulus format
2015-11-02 20:51:03 -05:00
Andreas Olofsson
96abfe3105
Initial register test (still debugging)
2015-11-02 19:27:41 -05:00
Andreas Olofsson
ec9c3d9e44
Delete old files
2015-11-02 16:08:14 -05:00
Andreas Olofsson
34d379ecb9
Adding new "simpler" test infrastruture
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- build elink with one command
- place all tests in tests/ directory
- new stimulus format followed
- dut_elink.v created
2015-11-02 16:04:46 -05:00
Andreas Olofsson
ccad681b0e
Fixing testbench for new clocks
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- Yay! Lots of logic removed
- elink passes again!!!
2015-10-07 19:21:36 -04:00
Andreas Olofsson
902ef1b7dd
Removing hack on rx clock
2015-09-30 13:00:14 -04:00
Andreas Olofsson
8c4c730682
added etype to elink instantiation
2015-09-27 08:40:09 -04:00
Andreas Olofsson
d7508f9938
DV cleanup
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-Set VCO_MULT to 1 for PLL. Dirty hack to allow the RX clk to phase align with the input. Otherwise, if you multiply the VCO clock and then divide, you get a random phase alignment the way the current clock divider is written.
-Changed the fifo_cdc to 32 entries. Forgot that I had changed the fifo_cdc to hard coded per number of entries. Really need to have a parametrixed model that works!!
2015-09-14 21:58:52 -04:00
Andreas Olofsson
31f6c94857
Removing random wait for now:
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-the read-after write is annoying
2015-09-14 20:22:18 -04:00
Andreas Olofsson
23e0f60388
cleanup
2015-09-14 13:28:44 -04:00
Andreas Olofsson
0bfd4d85fc
Adding sim parameter
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-lenth of reset pulse should be driven from sim environment
2015-09-11 18:25:08 -04:00
Andreas Olofsson
090a6c2b1e
Fixing interfaces due to moving idelay ctrl to clock block
2015-09-11 12:15:22 -04:00
Andreas Olofsson
d6f61784b0
Update dv paths
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-includes inside files (methodology change)
-adding ip paths
2015-07-02 16:48:14 -04:00
Andreas Olofsson
e28cd3cb97
Adding search path for include file
2015-07-02 16:47:07 -04:00
Andreas Olofsson
368836ab9b
Adding back a better fufu test vector
2015-07-02 16:46:33 -04:00
Andreas Olofsson
badac2aa76
Name changes for signal grouping
2015-06-25 16:09:05 -04:00
Andreas Olofsson
2cbf91b07b
Making reset sync in emmu
2015-05-23 22:26:15 -04:00
Andreas Olofsson
c9f64a2fb2
Fixing dv to check axi_elink
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-Need to split these, getting too cumbersome
2015-05-21 22:56:23 -04:00
Andreas Olofsson
a60de7fb30
Adding readback on axi_elink
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-Another cludgy memory
-Note that current esaxi doesn't support pushback so we have to hack the test to avoid read/write contention on this port.
2015-05-19 23:53:05 -04:00
Andreas Olofsson
6d9731f14a
Including environment for axi_elink
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-Should probably split this into separate environments
-Getting bulky and ugly...
2015-05-19 22:06:15 -04:00
Andreas Olofsson
665876cfb4
Adding bursting to test bench
2015-05-18 15:37:46 -04:00
Andreas Olofsson
007797169c
Clock and reset interface changes
2015-05-14 22:43:44 -04:00
Andreas Olofsson
4cd1e36537
Testbench update to include new clocking scheme
2015-05-13 23:30:30 -04:00
Andreas Olofsson
36696e709e
Updates for new interface
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-shortening to fit new clock
2015-05-12 07:42:56 -04:00
Andreas Olofsson
d83efbdb8e
Cleaning up initial constraints
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-Now generates bit stream
-It won't work, but it's a start...
2015-05-08 20:56:33 -04:00
Andreas Olofsson
38d7fe1af9
Clock cleanup
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-Moving to single clock
-Unifying the timescale (1ns period)
-Stopping access when done with stimulus file
2015-05-07 23:46:32 -04:00
