10 Commits

Author	SHA1	Message	Date
Andreas.Olofsson	9e9d323025	Changing the CFG_ASIC approach ... -Should be ifdef, since this is a global. You will never be doing and not an asic at the same time!	2020-02-04 23:04:52 -05:00
Andreas.Olofsson	21349445ef	Change macro name to reduce confusion	2020-02-04 22:43:18 -05:00
Andreas.Olofsson	d6f5de24d7	Changing hierarchy to promote blocks	2020-01-28 18:12:57 -05:00
Andreas Olofsson	7094173ae9	Reorg! Why? ... - The top level directory was not scaling, too imposing - Friendlier to download a repo and see a finite number of top level dirs - We are just getting started...	2016-03-22 08:13:40 -04:00
Andreas Olofsson	67afb87881	Cleaning up sp memory changes ... -removing incorrect bist dout port -repair vector name change	2016-02-26 17:01:24 -05:00
Andreas Olofsson	d0171fd1d8	Adding ASIC interface to single port memory ... - Yes, I know this means more signals for others to "ignore". The fpga way to handle this is to auto generate hierarchy to hide the signals. - I prefer a flatter structure with signals tied off and a library of known good components in a repo!	2016-02-26 16:31:09 -05:00
Andreas Olofsson	d4c5118a72	Making single/dual port memory interfaces constistant	2016-01-11 15:06:22 -05:00
Andreas Olofsson	d5d315b5b9	Adding missing parameter	2016-01-10 11:59:14 -05:00
Andreas Olofsson	3a8f81d4a3	Changing single port memory to be ASIC friendly	2015-12-03 18:01:21 -05:00
Andreas Olofsson	19fa611bb9	Massive reorganization to impove reuse ... - adding more chip code - pushing memory stuff into common - making common "oh_" naming class -	2015-11-30 13:45:49 -05:00