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329 Commits 7 Branches 1 Tag
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6 Commits

Author SHA1 Message Date
Andreas Olofsson
6ba45155fd Integrating clock approach change 
-clocks moved outside elink
-new packet interface format between protocol and io block
 2015-05-13 23:29:18 -04:00
Andreas Olofsson
fa374e666a Cleanup 2015-05-09 08:57:49 -04:00
Andreas Olofsson
a52fa86edb Fixing instances errors from fpga synthesis 2015-05-08 20:55:31 -04:00
Andreas Olofsson
1f6c18a764 Using fifo_cdc instead of fifo_async 2015-05-07 23:45:36 -04:00
Andreas Olofsson
ba32323306 Cleaning up clocks 
-moving to "real" Xilinx PLL instantiation
-one PLL for CCLK one for LCLK
-removing clock dividers, can't work at speed, put inside model
-configuration needs to be done differently
-removing pll_bypass signal, can't work with logic
-clocks should be done with hard macro primitives (no logic)
 2015-05-06 12:23:15 -04:00
Andreas Olofsson
d0439f871f Adding example design for FPGA 2015-05-05 21:37:17 -04:00