Andreas Olofsson
e622aa1b33
Reorg
2016-03-08 15:49:54 -05:00
Andreas Olofsson
197e2a38bc
Putting simplified scripts in $OH_HOME
2016-03-08 15:49:15 -05:00
Andreas Olofsson
789aa888a5
Filtering out
2016-03-08 14:58:21 -05:00
Andreas Olofsson
8e5f209115
Implemented parametrized spi slave module
...
- Compiles, but not debugged yet! (needs cleanup)
- Next up : implement master, testbench
2016-03-07 22:47:17 -05:00
Andreas Olofsson
983caa7138
Adding code pointers to readme
2016-03-05 16:42:41 -05:00
Andreas Olofsson
232d004ee2
Adding README for gpio
2016-03-05 16:36:58 -05:00
Andreas Olofsson
1ebe74d285
Cleanup GPIO logic
...
-various bringup bug fixes
-name simplication
-now works in simulation
2016-03-05 16:16:22 -05:00
Andreas Olofsson
53838f35ea
Added test/dv for gpio block
...
-note: with the number of blocks growing, there really needs to be more common iinfrastructure around the builds
-every block should be independent, yet you don't want to repeat the scripts
2016-03-05 16:10:06 -05:00
Andreas Olofsson
16ddde2e39
Fixing up GPIO
...
- adding support for 64 bits
- implementing global edge detect
- implementing most of the features
- (not debugged yet)
2016-03-05 07:28:28 -05:00
Andreas Olofsson
7a756decf8
Scary blocking call issue
...
- Can't believe this has been there for 4 gens of epiphany!
- Found it by chance when copying code over to edge detect...
2016-03-05 07:25:13 -05:00
Andreas Olofsson
4dbf1a201e
Adding configurable edge detector
2016-03-05 07:24:53 -05:00
Andreas Olofsson
5b6e89cb91
Merge pull request #54 from wasserfuhr/patch-1
...
Update README.md: typo
2016-03-01 21:53:47 -05:00
Andreas Olofsson
be9dd64650
Merge pull request #55 from wasserfuhr/patch-2
...
Update README.md: typo
2016-03-01 21:53:34 -05:00
RainerWasserfuhr
51976673c9
Update README.md
...
typo
2016-03-02 03:06:25 +01:00
RainerWasserfuhr
eb01ecac71
Update README.md
...
typo
2016-03-02 02:25:02 +01:00
Andreas Olofsson
5576775902
Merge branch 'master' of https://github.com/parallella/oh
2016-02-28 09:03:27 -05:00
Andreas Olofsson
56a4a64baf
Adding some missing defs from article feedback
2016-02-28 09:03:06 -05:00
Andreas Olofsson
844bc13d59
Removing ps7 file
...
-Not the right approach..
2016-02-27 13:37:36 -05:00
Andreas Olofsson
4630ef4033
Cleanup MIO commit
2016-02-26 23:08:14 -05:00
Andreas Olofsson
afb49073e4
Merge branch 'master' of github.com:parallella/oh
2016-02-26 23:01:04 -05:00
Andreas Olofsson
7d21ba64b7
Formatting
2016-02-26 23:00:53 -05:00
Andreas Olofsson
274f5f93c6
Renamed C2C to MIO
2016-02-26 22:51:35 -05:00
Andreas Olofsson
a5194a30a3
Reorg
...
-Renaming constants files as ".vh"
-Cleanup parameters
2016-02-26 19:08:40 -05:00
Andreas Olofsson
9aed3f19d2
Simplifying module
...
-Interrupt should be kept separate from GPIO (use PIC)
2016-02-26 19:06:38 -05:00
Andreas Olofsson
8cb368027c
Adding clkdivider model
...
-Modeling should be kept separate from real designs
2016-02-26 19:03:25 -05:00
Andreas Olofsson
3f3728b0bf
Removing timescale from file
...
-Nasty! Came out of nowhere, I guess compile order changed...
2016-02-26 19:02:43 -05:00
Andreas Olofsson
800c251717
Making target a parameter instead of 1/0
2016-02-26 17:15:39 -05:00
Andreas Olofsson
0437727d94
Adding new clocks to interface
2016-02-26 17:14:23 -05:00
Andreas Olofsson
3fc14dd0c1
Moving to "config" for IP
...
-Need to supply a config constant file at command line
(not with "include")
2016-02-26 17:13:20 -05:00
Andreas Olofsson
26474a40a7
Changed include file to ".vh"
2016-02-26 17:02:59 -05:00
Andreas Olofsson
67afb87881
Cleaning up sp memory changes
...
-removing incorrect bist dout port
-repair vector name change
2016-02-26 17:01:24 -05:00
Andreas Olofsson
a4f4881ccf
Adapting ememory to new single port memory interface
2016-02-26 16:59:41 -05:00
Andreas Olofsson
4a94d45750
Creating new "CLKDIV" module
...
-Model should be separate from design (very different needs)
2016-02-26 16:56:56 -05:00
Andreas Olofsson
d0171fd1d8
Adding ASIC interface to single port memory
...
- Yes, I know this means more signals for others to "ignore". The fpga way to handle this is to auto generate hierarchy to hide the signals.
- I prefer a flatter structure with signals tied off and a library of known good components in a repo!
2016-02-26 16:31:09 -05:00
Andreas Olofsson
c9e5336b5a
Formatting
2016-02-25 20:05:49 -05:00
Andreas Olofsson
090b6286d9
Wideneded scope of readme
2016-02-25 20:04:39 -05:00
Andreas Olofsson
5f9fea960a
Changing interface for consistency
...
-simple functions should strive for "in" and "out" parameters
2016-02-25 15:02:53 -05:00
Andreas Olofsson
1c0646c569
Implemented absolute value function
2016-02-25 15:00:33 -05:00
Andreas Olofsson
39f8115df8
Adding bitreverse module
2016-02-25 14:50:43 -05:00
Andreas Olofsson
701b1deca3
Bug fix: adding missing event on reset
2016-02-25 14:43:00 -05:00
Andreas Olofsson
4900f2c6e2
Propagating clock during reset
2016-02-25 14:42:39 -05:00
Andreas Olofsson
2a22cd6ff8
Removing delay + clock gating
...
- delay could hide bad designs..
- clock gating was hard to handle from outside
2016-02-25 14:41:30 -05:00
Andreas Olofsson
8f37435d95
Instantiating parallel CRC calculators
2016-02-25 14:40:38 -05:00
Andreas Olofsson
1fa1e05754
Adding parallel CRC generators from @alexforencich
2016-02-25 14:40:02 -05:00
Andreas Olofsson
87848d5a14
Parity operator
2016-02-25 10:56:35 -05:00
Andreas Olofsson
096dd728e4
Adding c2c description
2016-02-24 20:57:55 -05:00
Andreas Olofsson
387841bebd
Update README.md
2016-02-24 20:48:04 -05:00
Andreas Olofsson
dca2060895
Adding README file
2016-02-24 20:44:06 -05:00
Andreas Olofsson
96772b15f0
Adding new simplel chip to chip link
2016-02-24 20:29:56 -05:00
Andreas Olofsson
ddfb4e00de
Fixing generic fifo
...
- This one is looking better
- Still needs more review. At least now it has a testbench...
2016-02-24 14:26:25 -05:00
