Andreas Olofsson
cdef6141b4
Adding 2nd clock to interface
...
- Randomizeing clock frequencies
- Phase and frequency randomization a must for catching first order sync problems (and debunking really stupid ideas...)
- Don't be clever, be smart!
2016-02-24 14:23:30 -05:00
Andreas Olofsson
117a4fee0d
Doing forall "dut*.v"
...
- Adding entries to a list gets old real fast....
2016-02-24 14:22:32 -05:00
Andreas Olofsson
fc7dc0e70a
Adding "SEED" as basic parameter
...
-making randomness clocks a first class citizen
-Verilog doesn't have a seed, need to drive it from the shell
-a must for async clocks, useful for many things
-does not preclude randomization externally as well
2016-02-24 14:21:04 -05:00
Andreas Olofsson
bb4a602f7f
New "dut files"
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- new clocks (clk1 and 2)
- simpler names
- fifo dut
2016-02-24 14:19:57 -05:00
Andreas Olofsson
c9601a8f9c
Adding clk90 output to clkdiv
...
-Added testbench
-Needs more review!
2016-02-23 17:49:08 -05:00
Andreas Olofsson
84490be604
Adding testbench for clockdiv and gray converter
2016-02-23 17:17:41 -05:00
Andreas Olofsson
be22598935
Adding basic unit wiggle tests
2016-02-23 17:17:05 -05:00
Andreas Olofsson
8e466f3137
Adding debouncer circuit
2016-02-23 15:41:18 -05:00
Andreas Olofsson
c8b9de9f42
Adding gpio and spi paths
2016-01-24 23:42:06 -05:00
Andreas Olofsson
abd25426b6
Fixing various small bugs
...
-sandbox accelerator working in simulation!
-t0+6 hrs wall time (lost 2 hours due to travel)
2016-01-20 17:23:09 -05:00
Andreas Olofsson
ca5db9fa4d
Interface cleanup
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- fifo interface changes
- maxi/saxi name changes
- general code cleanup
- register remapping for mailbox
2016-01-19 13:33:08 -05:00
Andreas Olofsson
8d6c07be9b
Changing timeout
...
- Test being cut off too early.
- Really need to implement end of test indication already!!!
2016-01-13 15:32:15 -05:00
Andreas Olofsson
fa42bc6e2e
Reset simulation issue
...
- Feels like I have seen this before, but still makes me nervous. The async negedge of reset was never being triggered in simulation by iverilog, probably because the simulation initialized it to 0, so there was no negedge. In logic, this is an async level signal....
2016-01-11 20:47:06 -05:00
Andreas Olofsson
307794711d
Error message in one hot mux
2016-01-11 17:35:15 -05:00
Andreas Olofsson
4a454d71bd
Making AW main parameter
2016-01-11 15:05:21 -05:00
Andreas Olofsson
32522280e6
Cleanup
2016-01-10 15:58:28 -05:00
Andreas Olofsson
0568add03a
Changing emesh stimulus suffix ti "*.emf"
2016-01-10 11:57:38 -05:00
Andreas Olofsson
2672519ab0
Adding memory to driver
...
-More modular, foudn myself adding memories in a lot of places
2015-12-17 12:53:20 -05:00
Andreas Olofsson
f5bb42dfe3
Moving axi cells to own folder
2015-12-04 03:38:26 -05:00
Andreas Olofsson
9ddd71024d
Fixing system_bd interface for "mailbox_irq" signal
2015-11-29 12:41:53 -05:00
Andreas Olofsson
162cb022f9
Adding pushback circuit to stimulus
2015-11-24 01:04:14 -05:00
Andreas Olofsson
074186bd31
Adding new axi utility lib to sim file + README cleanup
2015-11-18 23:33:08 -05:00
Andreas Olofsson
75cef84075
Timescale stuff
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- Need to look into this again, gotchas here
-
2015-11-13 16:25:38 -05:00
Andreas Olofsson
3f1296b099
Cleanup
2015-11-12 10:50:05 -05:00
Andreas Olofsson
a9e034bef9
Bringing access low during wait
2015-11-12 00:58:06 -05:00
Andreas Olofsson
04cd179f5a
Lint fixes for icarus/verilator
2015-11-09 21:57:25 -05:00
Andreas Olofsson
55ba8ff635
Cleaning up warnings from FGPA tools
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- removing unconnected ports
- only one rst input for async_fifo
- synchronizing the reset input toe emaxi fifo
2015-11-09 13:23:40 -05:00
Andreas Olofsson
3969e6d19e
Moving to MIT license
2015-11-06 11:25:05 -05:00
Andreas Olofsson
751ad95a16
Adding parallella dir
2015-11-06 07:02:04 -05:00
Andreas Olofsson
92272e211d
Adding missind dirs in comamnd file
2015-11-04 20:04:44 -05:00
Andreas Olofsson
63e0017275
Stimulus end of test issue
...
- Still not 100% on this...but test passes
- Teset was hanging even though stim_done went high. Ticks not advancing, pointing towards comb loop, but what is different at end of test?
- Now to test read/writes of registers from axi and set the idelay registers
2015-11-03 19:56:27 -05:00
Andreas Olofsson
3f9ac4d745
Adding missing files
2015-11-03 14:16:50 -05:00
