Andreas Olofsson
36696e709e
Updates for new interface
...
-shortening to fit new clock
2015-05-12 07:42:56 -04:00
Andreas Olofsson
624d0e6134
Reorg cleanup
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-renamed disty for consistency (there is an arbiter there now)
-adding missing ID to etx/erx
-New org working!
2015-05-12 07:41:48 -04:00
Andreas Olofsson
fb96664a9c
Fixed width files doesn't work with .md files
2015-05-11 23:45:25 -04:00
Andreas Olofsson
5105790ff0
Adding address next to name
...
(ease of use)
2015-05-11 23:39:32 -04:00
Andreas Olofsson
bb37be52db
Updating elink register descritons
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-removing unused features
-updating register names
-updating structure
-simplifying protocol text
2015-05-11 23:18:21 -04:00
Andreas Olofsson
92fa02c44a
Wide image instead of centering..
2015-05-11 22:45:15 -04:00
Andreas Olofsson
12fd779558
Cropping image
2015-05-11 22:28:46 -04:00
Andreas Olofsson
b5e53f8196
Adding images, rearranging
2015-05-11 22:26:57 -04:00
Andreas Olofsson
a68a094285
Adding elink header image
2015-05-11 22:25:27 -04:00
Andreas Olofsson
3432c5fb45
Adding elink block diagram
2015-05-11 21:27:49 -04:00
Andreas Olofsson
81db0b7582
Completing elink hierarchy change
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-splits out clock domains
-makes the core portion a clean/reusable module with defined interface
2015-05-10 23:38:08 -04:00
Andreas Olofsson
d2b4dabc58
Moving chipid back to clocks
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-unnatural for it to be in etx
(link has nothing to do with epiphany id)
2015-05-10 23:35:41 -04:00
Andreas Olofsson
a627ecae7b
Removing testmode, bad idea
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-Should be input to fifo or etx_core
2015-05-10 23:35:04 -04:00
Andreas Olofsson
eaadfc6465
Adding etx/erx core modules
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-Single clock domain
-Super-light...
-Need to be able to remove internal feature as well
-(MMU/DMA should be optional but on by default..)
2015-05-10 23:06:52 -04:00
Andreas Olofsson
fa374e666a
Cleanup
2015-05-09 08:57:49 -04:00
Andreas Olofsson
eb3051ea93
Cleaning up logic to fit new access/packet interface
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(pre-debug)
2015-05-09 08:56:51 -04:00
Andreas Olofsson
ab26378a99
Adding elink with axi interfaces
2015-05-09 08:52:55 -04:00
Andreas Olofsson
d83efbdb8e
Cleaning up initial constraints
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-Now generates bit stream
-It won't work, but it's a start...
2015-05-08 20:56:33 -04:00
Andreas Olofsson
a52fa86edb
Fixing instances errors from fpga synthesis
2015-05-08 20:55:31 -04:00
Andreas Olofsson
9793be3bf0
Fixing crucial error in documentation
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-Nothing worse than incorrect comments!
2015-05-07 23:52:02 -04:00
Andreas Olofsson
38d7fe1af9
Clock cleanup
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-Moving to single clock
-Unifying the timescale (1ns period)
-Stopping access when done with stimulus file
2015-05-07 23:46:32 -04:00
Andreas Olofsson
1f6c18a764
Using fifo_cdc instead of fifo_async
2015-05-07 23:45:36 -04:00
Andreas Olofsson
c51f8f3dc9
Adding clock buffer
2015-05-07 23:44:39 -04:00
Andreas Olofsson
773bab5c6a
First version of synthesis tcl scripts for elink example
2015-05-07 23:43:05 -04:00
Andreas Olofsson
ba32323306
Cleaning up clocks
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-moving to "real" Xilinx PLL instantiation
-one PLL for CCLK one for LCLK
-removing clock dividers, can't work at speed, put inside model
-configuration needs to be done differently
-removing pll_bypass signal, can't work with logic
-clocks should be done with hard macro primitives (no logic)
2015-05-06 12:23:15 -04:00
Andreas Olofsson
4f487d498e
Making simulation more "real"
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-Working with timescale (for viewer mostly)
-Now using TARGET_XILINX as default in sim
2015-05-06 12:21:39 -04:00
Andreas Olofsson
d8b5fa78ef
Adding emesh as basic building block
2015-05-05 21:38:41 -04:00
Andreas Olofsson
d0439f871f
Adding example design for FPGA
2015-05-05 21:37:17 -04:00
Andreas Olofsson
c843fc5fe0
Renaming for my sanity (etx/erx split)
2015-05-05 14:56:35 -04:00
Andreas Olofsson
300e5a14fc
Reorg
2015-05-05 14:47:21 -04:00
Andreas Olofsson
a3cfa17b06
Removing old module
2015-05-04 22:38:28 -04:00
Andreas Olofsson
de74f8accc
Removed synchronizer, not needed
2015-05-04 22:34:14 -04:00
Andreas Olofsson
b2846c5312
MILESTONE: Read/write works back and forth
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-Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1
-Still not completely happy with reset (using async for now)
2015-05-04 17:13:51 -04:00
Andreas Olofsson
570fbffd7f
Baking in the IO wait signal into rd/wr wait
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-Separate waits for rd/wr wait
-Adding wait to protocol block as well
-io_wait always goes through
-using active frame signal to select/clear data for output
2015-05-04 17:10:32 -04:00
Andreas Olofsson
dcf72537e4
Separate rd/wr stalls
2015-05-04 17:09:50 -04:00
Andreas Olofsson
0aba754b7e
Cleanup
2015-05-04 10:54:42 -04:00
Andreas Olofsson
72aff72558
MILESTONE: register read/write working!
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-Bullet proof clock domain crossings!
2015-05-04 10:49:17 -04:00
Andreas Olofsson
bb8f5f861b
Moving the read response to separate group (not register)
...
Why?
1.) This will allow for support of multiple outstanding channels at some point
2.) Much easier to debug, can tag transactions in test bench
2015-05-04 10:41:42 -04:00
Andreas Olofsson
e9d6794833
Blocking TX outgoing transcations on LINKID match
2015-05-04 10:41:14 -04:00
Andreas Olofsson
25b0b188ff
Implementing register readback on read response channel
2015-05-04 10:40:43 -04:00
Andreas Olofsson
6907d39490
Making readback work
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-Simplifying logic for rx_en
-Reaback data was incorrectly pipelined (one too many)
2015-05-04 10:39:01 -04:00
Andreas Olofsson
b63de8b1d8
Filter the txwr access
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We don't want reset/clock transaction to propagate through etx!
2015-05-04 10:37:27 -04:00
Andreas Olofsson
1ee720fc67
Organization changes
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-dma with packet format
-using the fifo_cdc block
2015-05-03 23:29:32 -04:00
Andreas Olofsson
51b14f41ce
wait in vs. wait out confusion
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wait_out is the signal being driven out telling someone else to wait
wait_in is the incoming signal telling "you" to wait".
2015-05-03 23:26:43 -04:00
Andreas Olofsson
cfe811e7a7
Complete redesign
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-Following access,wait, packet pipeline format
-Use a priority arbiter
2015-05-03 23:25:19 -04:00
Andreas Olofsson
47a143eada
Turning on clocks by default (low frequency)
...
Seems safer
2015-05-03 23:23:28 -04:00
Andreas Olofsson
781121fc61
Cleanup
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-setting DMA access to zero for now
-taking away wait for elink2 (messes up the access pattern)
-fixing typo in register mape ERX
2015-05-02 23:04:13 -04:00
Andreas Olofsson
2da588721a
Fixed verilog syntax issue
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-Not sure what parameter couldn't be used directly here?
-Works fine when parameter is assigned to wire.
2015-05-02 23:03:14 -04:00
Andreas Olofsson
dcd2d0b111
Clock/reset fixes
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-Making reset async
-lclk_div4 always on (makes reset safer, not a big loss)
-filtering non-matching transactions
2015-05-02 22:42:33 -04:00
Andreas Olofsson
cb9a1f50dd
Fixing ecfg_clocks
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-Was missing clock connection
-Adding ID to match only to the right transcations
2015-05-02 22:40:27 -04:00
