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mirror of https://github.com/aolofsson/oh.git synced 2025-01-17 20:02:53 +08:00

39 Commits

Author SHA1 Message Date
Andreas Olofsson
d9f18e7b58 DV cleanup
-removing all redundant build files, there must be only one...
2016-03-08 21:23:02 -05:00
Andreas Olofsson
cb0b0e933c Adding basic tests for small modules
(so that run.sh can runt out of top dir)
2016-03-08 21:21:41 -05:00
Andreas Olofsson
af55033d05 Adding dut for emailbox 2016-03-08 21:20:34 -05:00
Andreas Olofsson
26474a40a7 Changed include file to ".vh" 2016-02-26 17:02:59 -05:00
Andreas Olofsson
a2d3b1e4e0 Adding rd_count, prog_full to interface
- status now 32 bit register
- block writing on full
- block reading on empty
- route prog_full to wait pushback circuit
2016-01-20 10:48:44 -05:00
Andreas Olofsson
1f42630f1c Adding sync fifo for mailbox as option 2016-01-19 23:34:56 -05:00
Andreas Olofsson
ca5db9fa4d Interface cleanup
- fifo interface changes
- maxi/saxi name changes
- general code cleanup
- register remapping for mailbox
2016-01-19 13:33:08 -05:00
Andreas Olofsson
240e5b433c Moving mailbox registers to new addres
-Mailbox is a pretty useful little block, registers don't belong in the RX space
-Moved registers to the "MESH" group block at bits [10:8].
-Feel good about this, should not change...
-Has been tested  to work with test/test_regs.emf
-For new register address, see README.md

cc @olajep @peteasa
2016-01-16 14:44:35 -05:00
Andreas Olofsson
a68bba1572 Cleaning up register interface
- Removed the cfgif block, too confusing. There is a good lesson here. Probably the n'th time I that I have been overzealous about reuse. When you end up adding a parameter to a block that duplicates the logic 2X it's always better to create two separate blocks...
- Changed the register access interface to packet format
- Change the priority on the etx_arbiter to pick read responses first
- Removed redundant signals
- Took away the read resonse bypass on remap in tx for now..
- Removed defparams (convention)
- Unified wait signal on tx
- Fixed cfg wait
-
2016-01-11 17:35:53 -05:00
Andreas Olofsson
2279137d39 Merge branch 'master' of https://github.com/parallella/oh
Conflicts:
	emailbox/hdl/emailbox.v
2016-01-10 16:37:20 -05:00
Andreas Olofsson
32522280e6 Cleanup 2016-01-10 15:58:28 -05:00
Andreas Olofsson
b130ac8fea Making AW in emesh2packet / packet2emesh explicit parameter 2016-01-10 11:51:49 -05:00
Peter Saunderson
e4aa6224da Filter for mailbox accesses - ecfg_if mi_dout_mux must only have one active input on mi_cfg_en
Signed-off-by: Peter Saunderson <peteasa@gmail.com>
2015-12-19 18:45:54 +00:00
Andreas Olofsson
5ddf9305a3 More packet interface changes... 2015-12-17 12:52:27 -05:00
Andreas Olofsson
7b8460b145 Fixing up issues with database reorg
- Not sure where the prog_full issue popped up from. (sign of disorganized databsae)
-
2015-11-30 15:07:28 -05:00
Andreas Olofsson
3ce9b41726 Working mailbox!
- Gating mailbox_not empty with irq_en. bit [28] of RXCFG
- Changing elink output interrupt to "or" of not_empty and full
- Adding mailbox status register (mostly for debug)
- Moving register addresses to make space for mailbox status register
- Fixing wrappers for DV
- Updating README docs with new register map
- Removing mailbox from RX status reg. Doesn't belong there, should be coupled with mailbox for modularity.
2015-11-29 12:20:17 -05:00
Andreas Olofsson
c294ba7775 Fixing readback from mailbox 2015-11-28 21:41:18 -05:00
Andreas Olofsson
04cd179f5a Lint fixes for icarus/verilator 2015-11-09 21:57:25 -05:00
Andreas Olofsson
19f773839d Fixed bug with packet decode
- mailbox write now working
2015-11-09 20:37:17 -05:00
Andreas Olofsson
bf614a9873 Cleaning up fifo interface
- removing redundant signals
- configuring to put synchronizer inside fifo
- one reset only (not two)
2015-11-09 13:20:46 -05:00
Andreas Olofsson
63bf5d25a4 Moving to active low reset
- Because this is the right thing to do for chips
- Not going to tell you why...
2015-11-06 16:51:57 -05:00
Andreas Olofsson
3969e6d19e Moving to MIT license 2015-11-06 11:25:05 -05:00
Andreas Olofsson
ff3af0b21c Fixing include files for emailbox
- All "folders" should be independent
2015-11-02 16:15:20 -05:00
Andreas Olofsson
62f5490f6b Adding missing file for emailbox 2015-11-01 16:45:39 -05:00
Andreas Olofsson
8a9b2e1b76 Separating rd/wr reset signals (proper) 2015-10-08 10:40:29 -04:00
Andreas Olofsson
f42b34ea3c Moving back to async reset 2015-10-07 19:21:04 -04:00
Andreas Olofsson
c627827a6b Fifo cleanup
-Adding model (one source..)
-generate for 104x32 for xilinx
-making prog_full the default full indicator
-bringing out almost_full for future use
-fixing interface change in all modules
2015-07-02 16:59:38 -04:00
Patrik Lindström
634ff371ac Bug fixes 2015-06-30 13:32:05 +02:00
Andreas Olofsson
b2b7f96e86 Making FIFO/memories easier to use
-WIDTH/DEPTH parameters
-Removing references to "clean" in ifdefs
2015-05-07 23:50:34 -04:00
Andreas Olofsson
b2846c5312 MILESTONE: Read/write works back and forth
-Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1
-Still not completely happy with reset (using async for now)
2015-05-04 17:13:51 -04:00
Andreas Olofsson
b375aaeb07 Adding back emesh access
-Write from emesh, read from mi.
-Final decision?
-Make readback 64 bits.
2015-05-04 10:36:07 -04:00
Andreas Olofsson
1c14ccd5d9 Generalizing emailbox
-There should be two clocks
(even though there is only one clock in erx)
2015-05-01 17:34:04 -04:00
Andreas Olofsson
395a1b3cb7 Merge branch 'master' of https://github.com/parallella/oh
Adding complete register documentation

Conflicts:
	elink/README.md
2015-04-29 11:55:01 -04:00
Andreas Olofsson
f544c44a08 Adding register access from RX
-Access without symmetry was awkward, now we can reach regs from TX or RX side
-Removes a special path for mailbox (came for free)
-At the same time reduced clock complexity (one clock for system!!)
-Moved mailbox to top level
-Changed main clock to "sys_clk" for all
2015-04-27 23:51:00 -04:00
Andreas Olofsson
c0d8c967c4 Address remapping integration
Integrated remapping logic (compiles)
Starting debug tomorrow...
2015-04-24 17:39:05 -04:00
Andreas Olofsson
370034437f Added proper 64bit write port to mailbox 2015-04-23 23:14:04 -04:00
Andreas Olofsson
0f0ff55928 Verilator based lint cleanup 2015-04-23 18:57:55 -04:00
Andreas Olofsson
155f6a9401 File cleanup 2015-04-23 18:10:07 -04:00
Andreas Olofsson
31e721cea7 Interface change
Changed to packet interface
Changed name to "mailbox"
2015-04-23 17:54:59 -04:00