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286 Commits 7 Branches 1 Tag
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5 Commits

Author SHA1 Message Date
Andreas Olofsson
b2846c5312 MILESTONE: Read/write works back and forth 
-Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1
-Still not completely happy with reset (using async for now)
 2015-05-04 17:13:51 -04:00
Andreas Olofsson
b63de8b1d8 Filter the txwr access 
We don't want reset/clock transaction to propagate through etx!
 2015-05-04 10:37:27 -04:00
Andreas Olofsson
47a143eada Turning on clocks by default (low frequency) 
Seems safer
 2015-05-03 23:23:28 -04:00
Andreas Olofsson
dcd2d0b111 Clock/reset fixes 
-Making reset async
-lclk_div4 always on (makes reset safer, not a big loss)
-filtering non-matching transactions
 2015-05-02 22:42:33 -04:00
Andreas Olofsson
e168bd5f98 reorg 2015-05-01 17:21:45 -04:00