4 Commits

Author	SHA1	Message	Date
Andreas Olofsson	21f87edd87	Memory bug fix ... -srcaddr (upper data of read response) was using input instead of output data -blocking upper data on 32 bit reads and smaller (quieter..) Need random DV to flush out these silly bugs...	2015-04-26 08:29:50 -04:00
Andreas Olofsson	3b637e55f0	MILESTONE: Design once again passes test ... New features: DMA MAILBOX directly in RX path TXMMU	2015-04-23 23:16:03 -04:00
Andreas Olofsson	ec0c9ce835	Changing to packet interface	2015-04-23 18:07:27 -04:00
Andreas Olofsson	0d42736914	Implemented enesh memory ... -not parametrized -keeping 64 bit wide for now	2015-04-21 17:13:09 -04:00