Andreas Olofsson
cd17b8130d
Adding support for 64core board
2016-01-13 15:32:46 -05:00
Andreas Olofsson
8d6c07be9b
Changing timeout
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- Test being cut off too early.
- Really need to implement end of test indication already!!!
2016-01-13 15:32:15 -05:00
Andreas Olofsson
c6bf2e2bb9
Removing "bid" parameter from emmu
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-Access signal decoded from outside
2016-01-13 15:31:38 -05:00
Andreas Olofsson
6f6413eddc
Updated regs test
2016-01-13 15:30:37 -05:00
Andreas Olofsson
b5179a097d
Cleanup
2016-01-13 15:30:15 -05:00
Andreas Olofsson
17431aefa0
Initial commit of open verilog reference
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-Work in progress!!!
2016-01-12 09:11:15 -05:00
Andreas Olofsson
b56da83aeb
Clarifying R/W permissions on some registers
2016-01-12 09:02:37 -05:00
Andreas Olofsson
57c44bafb1
Fixing MMU write access
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- MMU was being written when it shouldn't
2016-01-12 09:02:00 -05:00
Andreas Olofsson
804edcbc67
Adding reset signal to burst
2016-01-12 09:00:36 -05:00
Andreas Olofsson
f283b87e9d
Adding elink_monitor
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- Burst not supported
2016-01-12 08:38:45 -05:00
Andreas Olofsson
2bbe1e11b1
Change to TXCFG register!
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- Made room for extra bit in ctrlmode register
2016-01-11 21:35:57 -05:00
Andreas Olofsson
34d1049bab
Adding list of resources
2016-01-11 20:51:27 -05:00
Andreas Olofsson
bed1ba5556
Fixing write to TX register bug
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- The write transaction was incorrectly piped through to axi slave
2016-01-11 20:50:40 -05:00
Andreas Olofsson
99e58fb56e
Adding reset to pipeline
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- More conservative (only 2 more flops)
2016-01-11 20:49:31 -05:00
Andreas Olofsson
fa42bc6e2e
Reset simulation issue
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- Feels like I have seen this before, but still makes me nervous. The async negedge of reset was never being triggered in simulation by iverilog, probably because the simulation initialized it to 0, so there was no negedge. In logic, this is an async level signal....
2016-01-11 20:47:06 -05:00
Andreas Olofsson
a68bba1572
Cleaning up register interface
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- Removed the cfgif block, too confusing. There is a good lesson here. Probably the n'th time I that I have been overzealous about reuse. When you end up adding a parameter to a block that duplicates the logic 2X it's always better to create two separate blocks...
- Changed the register access interface to packet format
- Change the priority on the etx_arbiter to pick read responses first
- Removed redundant signals
- Took away the read resonse bypass on remap in tx for now..
- Removed defparams (convention)
- Unified wait signal on tx
- Fixed cfg wait
-
2016-01-11 17:35:53 -05:00
Andreas Olofsson
307794711d
Error message in one hot mux
2016-01-11 17:35:15 -05:00
Andreas Olofsson
d1062fbff8
Changing dp memory interface in calling module
2016-01-11 17:34:35 -05:00
Andreas Olofsson
d4c5118a72
Making single/dual port memory interfaces constistant
2016-01-11 15:06:22 -05:00
Andreas Olofsson
4a454d71bd
Making AW main parameter
2016-01-11 15:05:21 -05:00
Andreas Olofsson
152ee815e3
Making default 32bit for ease of use
2016-01-11 15:04:20 -05:00
Andreas Olofsson
1d540e7b49
Adding comments to table
2016-01-10 17:06:08 -05:00
Andreas Olofsson
eb8a29285d
Cleanup
2016-01-10 16:45:16 -05:00
Andreas Olofsson
2279137d39
Merge branch 'master' of https://github.com/parallella/oh
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Conflicts:
emailbox/hdl/emailbox.v
2016-01-10 16:37:20 -05:00
Andreas Olofsson
32522280e6
Cleanup
2016-01-10 15:58:28 -05:00
Andreas Olofsson
5f16bd672e
Changing test extension to "*emf"
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- The last field is a delay argument for stimulus
2016-01-10 15:55:58 -05:00
Andreas Olofsson
becff479ca
Refactoring (methodology)
2016-01-10 15:19:27 -05:00
Andreas Olofsson
c1da2531e6
Formatting
2016-01-10 15:18:40 -05:00
Andreas Olofsson
2feced7041
Methodology clarification
2016-01-10 15:16:24 -05:00
Andreas Olofsson
3168228174
Adding functionality for various modules
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(Work in progress, not tested)
2016-01-10 13:33:31 -05:00
Andreas Olofsson
d5d315b5b9
Adding missing parameter
2016-01-10 11:59:14 -05:00
Andreas Olofsson
55eeafe0db
Compile cleanup
2016-01-10 11:58:54 -05:00
Andreas Olofsson
0568add03a
Changing emesh stimulus suffix ti "*.emf"
2016-01-10 11:57:38 -05:00
Andreas Olofsson
b130ac8fea
Making AW in emesh2packet / packet2emesh explicit parameter
2016-01-10 11:51:49 -05:00
Andreas Olofsson
8b257066b3
Adding 64-bit support in packet format
2016-01-10 11:50:23 -05:00
Andreas Olofsson
fa09982df3
Merge pull request #27 from peteasa/mailbox_sw_with_interrupt_handling
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Updated mailbox test software and added trial kernel files
2015-12-20 15:05:25 -05:00
Andreas Olofsson
bb53768ce4
Merge pull request #26 from peteasa/mailbox_mi_dout_filter
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Filter for mailbox accesses - ecfg_if mi_dout_mux must only have one …
2015-12-20 15:05:01 -05:00
Peter Saunderson
a442dd4171
Updated mailbox test software and added trial kernel files
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Signed-off-by: Peter Saunderson <peteasa@gmail.com>
2015-12-20 19:59:35 +00:00
Peter Saunderson
e4aa6224da
Filter for mailbox accesses - ecfg_if mi_dout_mux must only have one active input on mi_cfg_en
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Signed-off-by: Peter Saunderson <peteasa@gmail.com>
2015-12-19 18:45:54 +00:00
Andreas Olofsson
9c9239d3ef
Summary of OH coding methodology
2015-12-17 22:11:27 -05:00
Andreas Olofsson
e9d3c78b17
Adding interfaces
2015-12-17 13:50:59 -05:00
Andreas Olofsson
3d49e9ef98
Making AW primary parameter
2015-12-17 12:53:48 -05:00
Andreas Olofsson
2672519ab0
Adding memory to driver
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-More modular, foudn myself adding memories in a lot of places
2015-12-17 12:53:20 -05:00
Andreas Olofsson
167744d7a9
Fixed data width
2015-12-17 12:52:49 -05:00
Andreas Olofsson
5ddf9305a3
More packet interface changes...
2015-12-17 12:52:27 -05:00
Andreas Olofsson
d558bd5f99
Packet converter interface changes
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-packet2emesh and emesh2packet had interface name changes
2015-12-17 12:51:22 -05:00
Andreas Olofsson
dbd8cd8044
Adding common module for write alignment
2015-12-17 12:37:41 -05:00
Andreas Olofsson
79c312d166
Cleanup
2015-12-17 12:36:02 -05:00
Andreas Olofsson
3708417934
Reuse refactoring
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-Made AW primary parameter to make reuse possible with other design
-Insert TARGET_SIM ifdef to make design synthesizable
2015-12-17 12:34:32 -05:00
Andreas Olofsson
27d7b0ed7c
Cleaning up code
2015-12-17 12:34:03 -05:00
