Use IRQ_F2P for interrupts, this is what other designs seem to do.
Use interrupt pin 11 (maps to IRQ=87 devicetree-IRQ=55 (87-32)).
Disable CORE0_FIQ_INTR as we no longer use it.
Add concat ip, apparently needed:
http://www.xilinx.com/support/answers/58942.html
Add constant_zero, and constant_one outputs to parallella_base module.
Tie all unused (by PL) interrupts on the F2P port to 0.
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
- reduced frame fanout, removed clock gater in erx_io (improves speed path)
- driving constants on "wid signals" (proper)
- making lock signal 1 bit wide to remove warning
- moved backed to BUFIO for IDDR blocks
