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9 Commits

Author SHA1 Message Date
Andreas Olofsson
57702798e5 Changing testbench to reflect real design
- The axi slave can never drive enough reads to saturate the maxi fifo since it's only sending out one read at a time.
- Changing the system so that a raw elink sits in front of stimulus..
2015-11-18 23:52:10 -05:00
Andreas Olofsson
c8b931efb0 Improving the elink_axi environment
- Turns out there was a bug hidden in the emaxi that can only be found by properly driving a master device with reads. This could not happen in the old environment.
- Note that due to limitations in the esaxi, I had to add the etx_fifo block as an interface (simplest).
- The ESAXI is very limited in that it MUST interface to a fifo with spare entries. (so prog_full). This should be FIXED!
- Minimal test passes, now to try to reproduce the DMA bug..
2015-11-18 23:26:59 -05:00
Andreas Olofsson
8820c8500a Adding wait circuit for axi/elink 2015-11-12 10:47:52 -05:00
Andreas Olofsson
867b750c50 Adding write from stimulus to dv link1
- also, more cleanup of ID parameters
2015-11-11 14:02:02 -05:00
Andreas Olofsson
6dcd5e96bf Cleanup after lock width change for zynq axi 2015-11-09 20:39:16 -05:00
Andreas Olofsson
63bf5d25a4 Moving to active low reset
- Because this is the right thing to do for chips
- Not going to tell you why...
2015-11-06 16:51:57 -05:00
Andreas Olofsson
3969e6d19e Moving to MIT license 2015-11-06 11:25:05 -05:00
Andreas Olofsson
6b83cdb0d7 Testbench bug fix
- can't connect a 64 bit interface to a 32bit one...
- (abuse of emaxi..)
2015-11-03 21:50:26 -05:00
Andreas Olofsson
f849f2410f Adding infrastructure for axi_elink
- Need to clean up some of these files later
2015-11-03 19:52:08 -05:00