Andreas Olofsson
f7806821c7
Various wait cleanups in RX
...
- using rx reset, safer as this stays in reset longer, until the clock has hade time to clean up the rest
2015-11-13 16:28:40 -05:00
Andreas Olofsson
55ba8ff635
Cleaning up warnings from FGPA tools
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- removing unconnected ports
- only one rst input for async_fifo
- synchronizing the reset input toe emaxi fifo
2015-11-09 13:23:40 -05:00
Andreas Olofsson
63bf5d25a4
Moving to active low reset
...
- Because this is the right thing to do for chips
- Not going to tell you why...
2015-11-06 16:51:57 -05:00
Andreas Olofsson
3969e6d19e
Moving to MIT license
2015-11-06 11:25:05 -05:00
Andreas Olofsson
8e32299f2c
Copyright cleanup
2015-08-07 09:19:37 -04:00
Andreas Olofsson
9379484f65
Fifo parameter change
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-Changing parameter name to DW
-Making depth 32 for axi interfaces
(tune this later...)
2015-07-02 16:55:42 -04:00
Andreas Olofsson
d2dcc15c52
Reset and clock cleanup
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-In the default mode we now have 7 input clocks to basic elink
-This is too many, need to simplify, not reasonable!
-But with all the knobs on the MMCM, performance will be great...
-WIP on bursting...
2015-05-14 22:31:42 -04:00
Andreas Olofsson
81db0b7582
Completing elink hierarchy change
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-splits out clock domains
-makes the core portion a clean/reusable module with defined interface
2015-05-10 23:38:08 -04:00
