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449 Commits 7 Branches 1 Tag
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207 Commits

Author SHA1 Message Date
Andreas Olofsson
58226bc867 Returned erx_io to old format! 
-Burst works again!
-There was definitely a bug on the frame signal, need to pay close attention to all the clock signals, let's review!
 2015-09-14 22:02:16 -04:00
Andreas Olofsson
0415b01753 Clock changes 
-separated PLL and MMCM
-rx clock only on PLL
-removed lock (fix further)
-simplified parameters, more intuitive to change
 2015-09-14 20:25:12 -04:00
Andreas Olofsson
23e0f60388 cleanup 2015-09-14 13:28:44 -04:00
Andreas Olofsson
0bfd4d85fc Adding sim parameter 
-lenth of reset pulse should be driven from sim environment
 2015-09-11 18:25:08 -04:00
Andreas Olofsson
c00003e9a3 Changing clocks back: 
-txclk should depend on the sysclk not rxclk
 2015-09-11 18:24:00 -04:00
Andreas Olofsson
52cded4eb2 Fixing Icarus compile error 
-multi dimensional parameters not working
-trying with regs
 2015-09-11 12:08:46 -04:00
Andreas Olofsson
0ec0794bbd Filling in missing parameters 
-needed for Icarus verilog simulator
 2015-09-11 12:08:07 -04:00
Patrik Lindström
137d8bfdb0 Changing receiver clock 
Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>
 2015-09-01 16:11:52 +02:00
Patrik Lindström
1a642a31d6 Removing ephycard define 
Signed-off-by: Patrik Lindström <patrik.lindstrom@foi.se>
 2015-08-25 12:40:48 +02:00
Patrik Lindström
5e8b10eafb Bug fixes 
Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>
 2015-08-24 22:50:28 +02:00
Patrik Lindström
98a17d6ccf Changing RX clocking 
Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>
 2015-08-24 22:39:51 +02:00
Patrik Lindström
9d71189f93 Changing the receiver to use both frame signals 
Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>
 2015-08-24 21:39:31 +02:00
Patrik Lindström
f9c2a5abf3 moving idelay controller to eclocks.v 
Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>
 2015-08-24 21:08:49 +02:00
Andreas Olofsson
9bc40a8355 Fixing wait issue 
-Removing the wait signal from the pipeline
-Assumption is that the prog_full is used on fifo, allowing two entries
to be captured in fifo.
-May revisit this at some time...
 2015-08-14 17:13:52 -04:00
Andreas Olofsson
ede8656081 Fixing mutual exclusive bug on receiver 
-When a read response is detected, there should be no spurious transactions to the RD/WR request fifos.
-Move the "filter" backt to the erx_protocol block
-Removed the remap bypass signal (was hacky)
-Passes simulations again..
 2015-08-14 15:37:37 -04:00
Andreas Olofsson
8e32299f2c Copyright cleanup 2015-08-07 09:19:37 -04:00
Andreas Olofsson
7df92eb1f0 Removing DMA from transmit 
* Seems like a useless feature. Why autogenerate the transactions at the transmit side. This should always be done at the receive side to minimize bits moving across the link.  Can't really see a use for it anymore so I am removing it.
* If you want to hack the design to reduce latency, you can always grab the raw etx_core and drive signals directly through write port.
* May consider adding a fourth port to etx to allow bypassing  the link interfac?
* Add an ifdef to bypass the fifos?
 2015-08-07 09:05:11 -04:00
Andreas Olofsson
36e8f78370 README changes and various fixes 2015-08-07 07:56:30 -04:00
Andreas Olofsson
9379484f65 Fifo parameter change 
-Changing parameter name to DW
-Making depth 32 for axi interfaces
(tune this later...)
 2015-07-02 16:55:42 -04:00
Andreas Olofsson
f1b37ab4c4 Ephycard should not be default 2015-07-02 16:54:31 -04:00
Patrik Lindström
a20c9f25ec clean up 2015-07-02 15:01:33 +02:00
Patrik Lindström
4a749bf2d8 timing fixes 2015-07-01 00:14:46 +02:00
Patrik Lindström
6d13611f21 script fixes 2015-06-30 16:02:39 +02:00
Patrik Lindström
667c7cb6a8 script fixes 2015-06-30 14:56:27 +02:00
Patrik Lindström
a284dff462 Bug fixes 2015-06-30 14:04:16 +02:00
Patrik Lindström
634ff371ac Bug fixes 2015-06-30 13:32:05 +02:00
Patrik Lindström
48fdf2d782 Added iostandard parameter 2015-06-30 12:44:22 +02:00
Patrik Lindström
f232d9d297 Changed rx_ref_clk PLL divider 2015-06-30 12:35:38 +02:00
Patrik Lindström
8c0dbffb61 Added different IDW for m_axi and s_axi 2015-06-30 12:31:14 +02:00
Andreas Olofsson
537bb6a330 Cleanup 2015-06-25 22:14:19 -04:00
Andreas Olofsson
badac2aa76 Name changes for signal grouping 2015-06-25 16:09:05 -04:00
Andreas Olofsson
24d824f080 Fixing read response address 
-using `define from elink_regmap (ie 'D')
 2015-05-20 15:04:29 -04:00
Andreas Olofsson
7f0f858b92 Letting read response packets through 
-Needed for loopback testing
 2015-05-20 15:03:22 -04:00
Andreas Olofsson
b1c3b3fb8c Adding filtering to ecfg_if 
-Avoids garbage writing coming back to esaxi
 2015-05-19 23:52:00 -04:00
Andreas Olofsson
005c9872dd Removing timeout from logic 
-Should be direct interface to esaxi
 2015-05-19 23:51:17 -04:00
Andreas Olofsson
7d524d0f68 Changing axi interface <--> elink protocol 
-Now consistant with packet, access, wait protocol
 2015-05-19 22:08:41 -04:00
Andreas Olofsson
8d3cbf8257 Clean axi_elink module 
-Clocks included inside for easy integration
-Another version might have the clocks and reset as inputs instead
 2015-05-19 22:07:16 -04:00
Andreas Olofsson
451a1fa925 MILESTONE: Bursts working!!! 
-Fairly clean minimalist design
-Complete redesign
-Need to do random read/write testing to make sure
-Speed?
 2015-05-18 15:38:30 -04:00
Andreas Olofsson
41f97e45ff Converting to synchronous reset 2015-05-17 23:00:53 -04:00
Andreas Olofsson
4fb6e7407c Integrating idelay elements in erx_io 2015-05-16 22:06:40 -04:00
Andreas Olofsson
017b72c37a MILESTONE: "almost final" block works! 
-bursting disabled, otherwise it looks good!
 2015-05-15 15:32:43 -04:00
Andreas Olofsson
d052da4ec9 Speed optimization 
-adding IDDR/ODDR blocks in IO
-still need to add the IDELAY controller and blocks
 2015-05-15 15:31:01 -04:00
Andreas Olofsson
9d3ecd0d06 Clock block cleanup 
-Moving TXCLK to CCLK domain, "feels cleaner"
-Also makes TXCLK independent of RXCLK
-So complete solution has a PLL and an MMCM
-Feeling is that the PLL for RXCLK could eventually be removed
-Need to add more state for locking clocks for receiver at end?
REVIEW!!!
 2015-05-15 15:28:19 -04:00
Andreas Olofsson
d2dcc15c52 Reset and clock cleanup 
-In the default mode we now have 7 input clocks to basic elink
-This is too many, need to simplify, not reasonable!
-But with all the knobs on the MMCM, performance will be great...
-WIP on bursting...
 2015-05-14 22:31:42 -04:00
Andreas Olofsson
77e210e7c2 Synchronous exit from reset 
-Async asert, sync deassert
-Haven't used this before.. (review?)
 2015-05-14 22:28:41 -04:00
Andreas Olofsson
d3d8f3f759 Clock and reset integration 
-moving clock and reset outside basic elink
-adding idelay reference clock
-separate and synchronized reset for each domain
-adding proper reset to fifo_cdc  (per domain, not asynch)
 2015-05-14 22:26:05 -04:00
Andreas Olofsson
1d848fe1d5 Making 2015-05-14 22:24:42 -04:00
Andreas Olofsson
5c690d38a1 Adding reset hardware state machine 
-concept developed by Gunnar Hillerstrom (VHDL)
-takes the driver out of the picture
-some people will run this bare metal
-more deterministic
-cuts down on hw/sw development issues
 2015-05-14 22:22:33 -04:00
Andreas Olofsson
a094f835c9 Rename (clarity) 
-file contains chip id, reset, and clocks
-base config driven by sys_clk
 2015-05-14 22:21:05 -04:00
Andreas Olofsson
befc18f368 MILESTONE: read/write works with all new RX/TX IO logic! 
-Fixes issue with back to back transactions!
-Read/writes work!!
-Needs more verification/analysis...
 2015-05-14 00:00:12 -04:00