- The top level directory was not scaling, too imposing
- Friendlier to download a repo and see a finite number of top level dirs
- We are just getting started...
- fixing msbfirst packet mode bug
- fixing lsbfirst packet mode bug
- fixing clkphase writing bug
- changing default to msb first
- making a single DEF_CFG and DEF_CLK parameters (it was getting out of hand)
- improved test to do emode/amode testing, and writing to registers
-"amode" now works!!**
-adding target parameter to fifo
-fixing rx protocol bugs
-adding defaults to register file, usually these should be set to zero and
-don't clock gate the DDR TX, just causes output to toggle like clock, BAD!
-fixed status register sticky bug
-adding autoincrement feature in amode
-fixing dut file for new "mio" subsystem
-**emesh packet now goes through in loopback!!!**
-Much easier to use and test, includes clockdiv and regs in one module
-Note that it's still possible to use the mio_dp raw if you tie off signals to constants and bring your own clock.
-Having both approachs should make everyone happy. Have found that SW developers usually can't write verilog and HW folks don't know C (so can't write to registers)...
- now includes mio regs as well
- next: create a complete block, ie dog fooding to include the mio_regs an axi interface, and a decoder interface to make it look like a subsystem (like the elink)
- These can be used to make the configuration of the mio datapath programmable
- This is what I should have done for the elink. Always separate the control from the datapath!!
