Andreas Olofsson
5e18ed8c52
Making defines unique
2015-11-06 22:33:33 -05:00
Andreas Olofsson
979b20a451
Fixing name on fileset for constraints
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- Apparantly has to be fixed to constr&^(I&W)%
2015-11-06 22:32:46 -05:00
Andreas Olofsson
ebf2e861de
Need to validate design before writing tcl
2015-11-06 20:47:35 -05:00
Andreas Olofsson
8b3fa77df1
Added missing index
2015-11-06 20:47:16 -05:00
Andreas Olofsson
1fa3543ba1
Changing back to lower cases, works..
2015-11-06 20:46:41 -05:00
Andreas Olofsson
a683e58597
Associating clock with bus interface
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- This should be moved to the block , block specific...
2015-11-06 20:45:38 -05:00
Andreas Olofsson
6e2ee17481
Updated system memory map
2015-11-06 20:44:18 -05:00
Andreas Olofsson
c9dc9c33ee
Almost done connecting
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- AXI connections not working properly...
2015-11-06 18:26:09 -05:00
Andreas Olofsson
63bf5d25a4
Moving to active low reset
...
- Because this is the right thing to do for chips
- Not going to tell you why...
2015-11-06 16:51:57 -05:00
Andreas Olofsson
322dc1119c
Adding standard modules for reset and data sync
2015-11-06 16:51:35 -05:00
Andreas Olofsson
8a89b7e185
Adding more structured vivado build files
2015-11-06 14:11:46 -05:00
Andreas Olofsson
84b5af5b3a
Cleanup
2015-11-06 14:10:35 -05:00
Andreas Olofsson
0a110f6e2c
Fixing contribution guidelines
2015-11-06 11:32:53 -05:00
Andreas Olofsson
7fcd0a366f
Adding contribution instructions
2015-11-06 11:31:16 -05:00
Andreas Olofsson
3969e6d19e
Moving to MIT license
2015-11-06 11:25:05 -05:00
Andreas Olofsson
8b2974feae
Massive reorg!
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- flattening hierarchy
- removing junk
2015-11-06 10:59:22 -05:00
Andreas Olofsson
e47fd56a21
Bulk edits (clean up later)
2015-11-06 07:03:28 -05:00
Andreas Olofsson
d15f67f470
Filtering more Xilinx crud
2015-11-06 07:02:47 -05:00
Andreas Olofsson
22a95292d3
Fixing empty models
2015-11-06 07:02:28 -05:00
Andreas Olofsson
751ad95a16
Adding parallella dir
2015-11-06 07:02:04 -05:00
Andreas Olofsson
0fcea92b0d
Scripts per "project"
2015-11-06 06:58:47 -05:00
Andreas Olofsson
90998b8ad0
Adding parallella synthesis scripts
2015-11-06 06:58:14 -05:00
Andreas Olofsson
6cb5f88073
Moving block deisgns into a single Parallella module
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- Easier to maintain
- Better sandbox
2015-11-06 06:56:56 -05:00
Andreas Olofsson
5086052cb5
Adding timing constraints
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- structure feels right
- one folder per reusable module
- everything should be contained within one "package"
2015-11-04 22:13:35 -05:00
Andreas Olofsson
81fe46a929
Removing xpr file
...
(everything done through tcl)
2015-11-04 22:12:50 -05:00
Andreas Olofsson
025af1ee54
Yay! Now runs to completion
2015-11-04 22:11:19 -05:00
Andreas Olofsson
ee6a9a93ac
Updating scripts
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- adding more compatibility families
2015-11-04 21:46:15 -05:00
Andreas Olofsson
92272e211d
Adding missind dirs in comamnd file
2015-11-04 20:04:44 -05:00
Andreas Olofsson
6a423b5999
Improcing mmcm/pll clock path
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-apparantly the BUFG in the feedback was not liked by the P&R
2015-11-04 20:02:45 -05:00
Andreas Olofsson
49bf52374d
Changing model to use parameter rather than tick-define
2015-11-04 20:01:31 -05:00
Andreas Olofsson
2ed60c5698
Merge branch 'master' of https://github.com/parallella/oh
2015-11-04 19:20:13 -05:00
Andreas Olofsson
3e78d06051
Moving models out of hdl
2015-11-04 19:20:03 -05:00
Andreas Olofsson
dbff2623c1
Cleanup
2015-11-04 19:18:45 -05:00
Andreas Olofsson
96efc91ec1
Filtering more Xilinx junk files
2015-11-04 19:18:11 -05:00
Andreas Olofsson
0cf23a8d1b
Reorg
2015-11-04 19:16:50 -05:00
Andreas Olofsson
81b71df54e
Reorg
2015-11-04 19:15:05 -05:00
Andreas Olofsson
8938c396b6
Merge pull request #15 from peteasa/packagingPathUpdates
...
Updated paths and added missing source
2015-11-04 17:57:49 -05:00
Andreas Olofsson
e763cc0250
Added filters for all the Xilinx junk
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- git should have only .tcl files really...
2015-11-04 17:55:01 -05:00
Andreas Olofsson
30077cc1e5
Scripted elink build script (version 0)
...
- starting to feel better about structure
2015-11-04 17:53:54 -05:00
Peter Saunderson
9009113162
Updated paths and added missing source
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Signed-off-by: Peter Saunderson <peteasa@gmail.com>
2015-11-04 20:14:57 +00:00
Andreas Olofsson
8a8255ddfd
Adding common scripts directory
2015-11-04 14:15:49 -05:00
Andreas Olofsson
6b83cdb0d7
Testbench bug fix
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- can't connect a 64 bit interface to a 32bit one...
- (abuse of emaxi..)
2015-11-03 21:50:26 -05:00
Andreas Olofsson
63e0017275
Stimulus end of test issue
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- Still not 100% on this...but test passes
- Teset was hanging even though stim_done went high. Ticks not advancing, pointing towards comb loop, but what is different at end of test?
- Now to test read/writes of registers from axi and set the idelay registers
2015-11-03 19:56:27 -05:00
Andreas Olofsson
6d9d9702d8
Simulation file cleanup
2015-11-03 19:53:43 -05:00
Andreas Olofsson
f849f2410f
Adding infrastructure for axi_elink
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- Need to clean up some of these files later
2015-11-03 19:52:08 -05:00
Andreas Olofsson
36b0f14ca5
"Fixing" wait signal
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- Giving a wait on every ack just doesn't make sense on the read port with a fifo there??
- Makes for a nasty combinatorial loop during integration.
- Test passes (but need to look into this more)
2015-11-03 19:49:38 -05:00
Andreas Olofsson
6114471935
Adding active signal to interface
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- kind of like "pll lock"
2015-11-03 19:49:09 -05:00
Andreas Olofsson
3f9ac4d745
Adding missing files
2015-11-03 14:16:50 -05:00
Andreas Olofsson
b4daf73157
Optimizing clock path
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* Sven's help!
* Better to use bufio to keep all paths internal, more determenistic path
2015-11-03 14:15:09 -05:00
Andreas Olofsson
fb45666b13
Adding idelay config register documentation
2015-11-03 10:46:05 -05:00
