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413 Commits 7 Branches 1 Tag
Commit Graph

190 Commits

Author SHA1 Message Date
Andreas Olofsson
a1722b7ae6 Adding timeout circuit 2015-04-27 16:02:15 -04:00
Andreas Olofsson
c9124f415b Added "timeout" to elink interface 
-Use as error interrupt?
-Is there another method for checking error?
 2015-04-27 15:11:56 -04:00
Andreas Olofsson
b0116c9316 Added read watchdog timer 
-A read on transmit side initiates timer
-Timer is reset when read request comes back
(assumption last read requests starts timer..last return stops it)
 2015-04-27 13:00:00 -04:00
Andreas Olofsson
3683c39e5b Bug fix. Fifo read delay not accounted for 
-Added valid signal to fifo
 2015-04-27 11:16:15 -04:00
Andreas Olofsson
4856e39193 RX address remap bug fix 
-Used the wrong sub vector...
(silly mistake)
 2015-04-27 09:29:22 -04:00
Andreas Olofsson
d79447853f Register name shuffle 2015-04-27 09:28:52 -04:00
Andreas Olofsson
3cb8d1d426 Adding test mode registers for transmit path 
Makes it possible to easily test the IO path using the mi_ interface
The mi interface is very simple to drive in logic...
 2015-04-27 00:04:30 -04:00
Andreas Olofsson
89286af8a9 Adding documentation of elink protocol 2015-04-26 23:02:13 -04:00
Andreas Olofsson
f7aef66f29 Bug fix: erx pipeline misalignment 
-access signal happens one signal after empty goes low to compensate for fifo data latency
-verify that this is how the Xilinx FIFO works as well.
 2015-04-26 08:31:36 -04:00
Andreas Olofsson
21f87edd87 Memory bug fix 
-srcaddr (upper data of read response) was using input instead of output data
-blocking upper data on 32 bit reads and smaller (quieter..)
Need random DV to flush out these silly bugs...
 2015-04-26 08:29:50 -04:00
Andreas Olofsson
afd6e86840 Fixing etx pipeline 
-Fixed one bug inserted during edits, causing double transactions
-Added pipeline stall logic to all units
 2015-04-25 23:28:52 -04:00
Andreas Olofsson
ca835b9607 tweaking register map again... 2015-04-25 23:28:18 -04:00
Andreas Olofsson
5f595a75d3 Register write bug for new map 
-Need to block access if [15] is one (reserved for emmurx)
 2015-04-25 07:10:13 -04:00
Andreas Olofsson
919a5fa5e8 Register map twiddles 
-Fixed test to correspond to new map
 2015-04-25 07:09:52 -04:00
Andreas Olofsson
c0d8c967c4 Address remapping integration 
Integrated remapping logic (compiles)
Starting debug tomorrow...
 2015-04-24 17:39:05 -04:00
Andreas Olofsson
be42ea3b89 Register map change 
-Changed register map
-Splitting into groups, more natural
 2015-04-24 17:38:01 -04:00
Andreas Olofsson
ea7683693c Adding RX/TX address remapping 
The MMU is a monster and may be too much
Adding simple remapping modules
Covers todays feature and then some
1.) Static remapping
2.) Addresss compression
 2015-04-24 17:29:05 -04:00
Andreas Olofsson
b25ad633f7 Readback cleanup 
RX/TX interfaces should be mininmized and standalone
Adding mux to consolidate to one "dout"
 2015-04-24 17:27:35 -04:00
Andreas Olofsson
3b637e55f0 MILESTONE: Design once again passes test 
New features:
DMA
MAILBOX directly in RX path
TXMMU
 2015-04-23 23:16:03 -04:00
Andreas Olofsson
0ed6afeac9 Added tag and group for read response 
-Still not sure about this..
 2015-04-23 23:14:39 -04:00
Andreas Olofsson
46896c63ef Bug fix, adding reset signal 
This will blocking when there is no clock at startup.
 2015-04-23 23:13:05 -04:00
Andreas Olofsson
24fc91072d Adding IDs to keep access signals straight 2015-04-23 23:11:58 -04:00
Andreas Olofsson
01fec0f72a Fixed elink missind ID parameter 2015-04-23 20:07:52 -04:00
Andreas Olofsson
5c8fb41849 Fifo read bug 
-fifo should be read when it's not empty and there is no wait pushback
 2015-04-23 20:07:10 -04:00
Andreas Olofsson
c4c1edc10f Adding reset to critical signals in pipe 2015-04-23 20:06:11 -04:00
Andreas Olofsson
7ab3b3a8f8 Fixed floating net bug 2015-04-23 20:05:00 -04:00
Andreas Olofsson
0f0ff55928 Verilator based lint cleanup 2015-04-23 18:57:55 -04:00
Andreas Olofsson
155f6a9401 File cleanup 2015-04-23 18:10:07 -04:00
Andreas Olofsson
842dd60b3e Adding DMA register to regmap 2015-04-23 18:08:52 -04:00
Andreas Olofsson
c76bce1ea3 Changing so basic elink unti is without AXI 2015-04-23 18:08:20 -04:00
Andreas Olofsson
fcf5bf010f Splitting register file into separate pieces 2015-04-23 18:07:50 -04:00
Andreas Olofsson
ec0c9ce835 Changing to packet interface 2015-04-23 18:07:27 -04:00
Andreas Olofsson
ed0b8c2539 Major RX change: 
-renamed interfaces to rxwr,rxrd,rxrr (much simpler to remember for me)
-packet interface change
-removed wait signals from dataout field
-added dma, emmu, mailbox, config register
-instantiating fifo_sync raw (without wrapper)
 2015-04-23 18:04:39 -04:00
Andreas Olofsson
2707541eab Adding DMA source and changing interface 
-DMA added as a master driving out transactions
(this is going to be great!!)
-Changing to packet interface
 2015-04-23 18:03:10 -04:00
Andreas Olofsson
842a6d894a Fixing enable/reset: 
-Removing enable from ISERDES, not healthy
-Moving all logic to protocol block. (this is an IO block)
-Removing tow redundant pipeline stages (check this??)
 2015-04-23 18:01:19 -04:00
Andreas Olofsson
7418d45f5e Cleanup 
-Packet interface change
-Adding RX enable logic with synchronizer  (better place than erx_io)
 2015-04-23 17:59:36 -04:00
Andreas Olofsson
d9525b6ae4 Major upgrade 
-Adding DMA, EMMU, CFG
-Removing redundant signals
-Changing to packet interface
 2015-04-23 17:58:18 -04:00
Andreas Olofsson
9a614d1094 Packet interface change 2015-04-23 17:57:24 -04:00
Andreas Olofsson
44f162ec09 Packet interface change 
-Changed packet interface
-Removed rd/wr from block, was pass through
 2015-04-23 17:56:15 -04:00
Andreas Olofsson
1e1644138e Splitting register file (rx,tx,base) 
The goal is to have 100% independence in RX and TX pipes
 2015-04-23 17:50:45 -04:00
Andreas Olofsson
cc5f165454 Clarified lclk names 2015-04-22 15:03:24 -04:00
Andreas Olofsson
703da8445b deleted junk 2015-04-22 15:02:31 -04:00
Andreas Olofsson
797d836a02 Renaming constants file 2015-04-22 13:56:48 -04:00
Andreas Olofsson
275264c84d Reorg 2015-04-21 21:33:49 -04:00
Andreas Olofsson
035b3c9ba5 Milestone: WRITE AND READ FROM HOST WORKS! 2015-04-21 17:16:20 -04:00
Andreas Olofsson
d0b04687ea Bug fix, missing pipeline stage on read response 
-Apparantly old FIFO was not pipelined (IE data comes back same cycle).
-Not knowing the Xilinx logic, I made it a regular one cycle pipeline
memory based FIFO
 2015-04-21 17:14:30 -04:00
Andreas Olofsson
0d42736914 Implemented enesh memory 
-not parametrized
-keeping 64 bit wide for now
 2015-04-21 17:13:09 -04:00
Andreas Olofsson
2369e92ffa Bug fix, missing "data hold" stage 
Hadn't realized that the data needed to be held
Need to look at this logic again!
For now going back to old logic
 2015-04-21 17:10:51 -04:00
Andreas Olofsson
e033e233d0 Integrating emesh memory module 
-This will flush out the final read response path
 2015-04-20 23:07:13 -04:00
Andreas Olofsson
4c44c59079 Message box working... 
-More testing needed!
 2015-04-19 21:55:07 -04:00