8 Commits

Author	SHA1	Message	Date
Andreas Olofsson	2e6130fd19	Adding valid signal to fifo ... -Since data has one pipeline delay, this makes it much easier to use -Matches better with Xilinx fifo generator	2015-04-27 11:15:06 -04:00
Andreas Olofsson	5ac06cd772	Fixed stupid typos on full/empty ... Surprised it wasn't caught during iverilog compile	2015-04-23 18:56:49 -04:00
Andreas Olofsson	34813035bc	Changing FIFO interface ... More inline with standard Xilinx fifo names, names, names..ugh	2015-04-23 17:53:22 -04:00
Andreas Olofsson	7bc3b662ab	Added profull HACK to async_fifo ... -this module needs rework -needs to have same capabilities as standard FPGA async fifos -remove this later	2015-04-17 15:49:58 -04:00
Andreas Olofsson	846bfa3357	Fixing startup issues in transmit path: ... -adding reset signals to synchronizer to solve startup issues -setting config in test bench for speedup, default reg config now correct -fix (my) stupid bug in etx_arbiter -adding reset to fifo (todo: review this!) -reviewing "all red" from waveforms is a must. Red (x) on data is ok, but leaving them on control signals is asking for trouble. Better safe than sorry when it comes to reset.	2015-04-15 16:33:20 -04:00
Andreas Olofsson	4fd4c8e989	Adding platform agnostic dual ported memory and async fifo	2015-04-14 23:56:00 -04:00
Andreas Olofsson	d2fc0da3a1	Fixing file permissions ... Verilog text files should not have execute permissions!	2015-04-08 13:26:12 -04:00
Andreas Olofsson	b0b9315bf1	Massive checkin... ... -this may break already broken projects -creates a Verilog top level (instead of using Vivado block level design) -integrates mmy and mailbox (not completely integrated) -compiles... -pours in all of the code from the archive (some new logic created)	2015-03-24 20:44:03 -04:00