9 Commits

Author	SHA1	Message	Date
Andreas Olofsson	61eb56c6f7	Final Vivado fixups: ... - reduced frame fanout, removed clock gater in erx_io (improves speed path) - driving constants on "wid signals" (proper) - making lock signal 1 bit wide to remove warning - moved backed to BUFIO for IDDR blocks	2015-11-09 16:09:12 -05:00
Andreas Olofsson	c84e1c96b7	Adding hdmi pins for parallella	2015-11-09 13:22:08 -05:00
Andreas Olofsson	9383f32764	Making sure ETYPE is set to 0.	2015-11-06 22:41:43 -05:00
Andreas Olofsson	8b3fa77df1	Added missing index	2015-11-06 20:47:16 -05:00
Andreas Olofsson	1fa3543ba1	Changing back to lower cases, works..	2015-11-06 20:46:41 -05:00
Andreas Olofsson	63bf5d25a4	Moving to active low reset ... - Because this is the right thing to do for chips - Not going to tell you why...	2015-11-06 16:51:57 -05:00
Andreas Olofsson	3969e6d19e	Moving to MIT license	2015-11-06 11:25:05 -05:00
Andreas Olofsson	8b2974feae	Massive reorg! ... - flattening hierarchy - removing junk	2015-11-06 10:59:22 -05:00
Andreas Olofsson	6cb5f88073	Moving block deisgns into a single Parallella module ... - Easier to maintain - Better sandbox	2015-11-06 06:56:56 -05:00