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mirror of https://github.com/aolofsson/oh.git synced 2025-01-30 02:32:53 +08:00

18 Commits

Author SHA1 Message Date
aolofsson
289024fd89 Flattening directory tree (again)
- Creating an arbitrary 'src' directory really doesn't help much...
- Goal is to make each folder self contained
- Make meta repos and individual repos have the same directory structure
2022-06-21 14:48:48 -04:00
aolofsson
e89f815b38 Going back to placing all folders in src
- Only way to scale, final decision!!
2022-05-29 08:45:00 -04:00
Andreas.Olofsson
d6f5de24d7 Changing hierarchy to promote blocks 2020-01-28 18:12:57 -05:00
Andreas Olofsson
7094173ae9 Reorg! Why?
- The top level directory was not scaling, too imposing
- Friendlier to download a repo and see a finite number of top level dirs
- We are just getting started...
2016-03-22 08:13:40 -04:00
Ola Jeppsson
cf4aa62027 Fix mailbox interrupt
Use IRQ_F2P for interrupts, this is what other designs seem to do.
Use interrupt pin 11 (maps to IRQ=87 devicetree-IRQ=55 (87-32)).

Disable CORE0_FIQ_INTR as we no longer use it.

Add concat ip, apparently needed:
http://www.xilinx.com/support/answers/58942.html

Add constant_zero, and constant_one outputs to parallella_base module.

Tie all unused (by PL) interrupts on the F2P port to 0.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
2016-01-20 22:30:56 +01:00
Andreas Olofsson
7b8460b145 Fixing up issues with database reorg
- Not sure where the prog_full issue popped up from. (sign of disorganized databsae)
-
2015-11-30 15:07:28 -05:00
Andreas Olofsson
9ddd71024d Fixing system_bd interface for "mailbox_irq" signal 2015-11-29 12:41:53 -05:00
Andreas Olofsson
038d39def7 Defparam typo
- Not caught by iverilog!! (file bug??)
- Caught by Vivado.
2015-11-11 14:13:38 -05:00
Andreas Olofsson
0a2ea66b7e Bug fix. Adding missing ID parameter.
- would only show up at different ID
- better to always make defauly nonsense
- sneaky...
2015-11-11 13:58:04 -05:00
Andreas Olofsson
61eb56c6f7 Final Vivado fixups:
- reduced frame fanout, removed clock gater in erx_io (improves speed path)
- driving constants on "wid signals" (proper)
- making lock signal 1 bit wide to remove warning
- moved backed to BUFIO for IDDR blocks
2015-11-09 16:09:12 -05:00
Andreas Olofsson
c84e1c96b7 Adding hdmi pins for parallella 2015-11-09 13:22:08 -05:00
Andreas Olofsson
9383f32764 Making sure ETYPE is set to 0. 2015-11-06 22:41:43 -05:00
Andreas Olofsson
8b3fa77df1 Added missing index 2015-11-06 20:47:16 -05:00
Andreas Olofsson
1fa3543ba1 Changing back to lower cases, works.. 2015-11-06 20:46:41 -05:00
Andreas Olofsson
63bf5d25a4 Moving to active low reset
- Because this is the right thing to do for chips
- Not going to tell you why...
2015-11-06 16:51:57 -05:00
Andreas Olofsson
3969e6d19e Moving to MIT license 2015-11-06 11:25:05 -05:00
Andreas Olofsson
8b2974feae Massive reorg!
- flattening hierarchy
- removing junk
2015-11-06 10:59:22 -05:00
Andreas Olofsson
6cb5f88073 Moving block deisgns into a single Parallella module
- Easier to maintain
- Better sandbox
2015-11-06 06:56:56 -05:00