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5 Commits

Author SHA1 Message Date
Andreas Olofsson
d7d959da45 Adding software programmable IDELAY
- This is DEFINITELY the way to do things, sweep the delays and find the right value. No f'ing way to get these stupid FPGAs to work otherwise with the ridiculuosly over margined PVT nubmers they are running through the STAs. I understand they want to make the design bullet proof, but as a result designers are wasting countless hours overoptimzinng designs and being clever. So much performance is left on the table for expert users.
- Lesson: I/O design should be "self syncrhonizing". Only contraints in the design should be create_clk
- Made RX clock async, too tricky to guarantee that there clock is there.  No way to do this if the clock sources are actually independent for RX/TX!
2015-10-07 11:49:46 -04:00
Andreas Olofsson
8e32299f2c Copyright cleanup 2015-08-07 09:19:37 -04:00
Patrik Lindström
634ff371ac Bug fixes 2015-06-30 13:32:05 +02:00
Andreas Olofsson
41f97e45ff Converting to synchronous reset 2015-05-17 23:00:53 -04:00
Andreas Olofsson
c843fc5fe0 Renaming for my sanity (etx/erx split) 2015-05-05 14:56:35 -04:00