FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-21 22:12:54 +08:00
Code Issues Projects Releases Wiki Activity
526 Commits 7 Branches 1 Tag
Commit Graph

348 Commits

Author SHA1 Message Date
Andreas Olofsson
0bfd4d85fc Adding sim parameter 
-lenth of reset pulse should be driven from sim environment
 2015-09-11 18:25:08 -04:00
Andreas Olofsson
c00003e9a3 Changing clocks back: 
-txclk should depend on the sysclk not rxclk
 2015-09-11 18:24:00 -04:00
Andreas Olofsson
090a6c2b1e Fixing interfaces due to moving idelay ctrl to clock block 2015-09-11 12:15:22 -04:00
Andreas Olofsson
52cded4eb2 Fixing Icarus compile error 
-multi dimensional parameters not working
-trying with regs
 2015-09-11 12:08:46 -04:00
Andreas Olofsson
0ec0794bbd Filling in missing parameters 
-needed for Icarus verilog simulator
 2015-09-11 12:08:07 -04:00
Ola Jeppsson
efb1eea253 README.md: ETX_CFG == 0xF0210 2015-09-07 19:50:28 +02:00
Patrik Lindström
137d8bfdb0 Changing receiver clock 
Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>
 2015-09-01 16:11:52 +02:00
Patrik Lindström
14beca6a8f Script fixes 
Signed-off-by: Patrik Lindström <patrik.lindstrom@foi.se>
 2015-08-25 18:21:19 +02:00
Patrik Lindström
8f144a050a Script fixes 
Signed-off-by: Patrik Lindström <patrik.lindstrom@foi.se>
 2015-08-25 18:17:30 +02:00
Patrik Lindström
abebbeb7dd Adding xgui 
Signed-off-by: Patrik Lindström <patrik.lindstrom@foi.se>
 2015-08-25 14:58:37 +02:00
Patrik Lindström
a5c160fc0d Script fixes 
Signed-off-by: Patrik Lindström <patrik.lindstrom@foi.se>
 2015-08-25 13:03:44 +02:00
Patrik Lindström
1a642a31d6 Removing ephycard define 
Signed-off-by: Patrik Lindström <patrik.lindstrom@foi.se>
 2015-08-25 12:40:48 +02:00
Patrik Lindström
5e8b10eafb Bug fixes 
Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>
 2015-08-24 22:50:28 +02:00
Patrik Lindström
98a17d6ccf Changing RX clocking 
Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>
 2015-08-24 22:39:51 +02:00
Patrik Lindström
9d71189f93 Changing the receiver to use both frame signals 
Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>
 2015-08-24 21:39:31 +02:00
Patrik Lindström
f9c2a5abf3 moving idelay controller to eclocks.v 
Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>
 2015-08-24 21:08:49 +02:00
Andreas Olofsson
9bc40a8355 Fixing wait issue 
-Removing the wait signal from the pipeline
-Assumption is that the prog_full is used on fifo, allowing two entries
to be captured in fifo.
-May revisit this at some time...
 2015-08-14 17:13:52 -04:00
Andreas Olofsson
ede8656081 Fixing mutual exclusive bug on receiver 
-When a read response is detected, there should be no spurious transactions to the RD/WR request fifos.
-Move the "filter" backt to the erx_protocol block
-Removed the remap bypass signal (was hacky)
-Passes simulations again..
 2015-08-14 15:37:37 -04:00
Andreas Olofsson
21686d31cc Reorg for xilinx projects 
-making more modular
-still need to clean up duplucate files
 2015-08-08 12:29:00 -04:00
Andreas Olofsson
b0a321a588 Clarified enable/disable status 
-For now RX/TX is always on
-At some point make default off?
 2015-08-07 09:25:41 -04:00
Andreas Olofsson
8e32299f2c Copyright cleanup 2015-08-07 09:19:37 -04:00
Andreas Olofsson
617e5f76de Updating interface description 2015-08-07 09:15:10 -04:00
Andreas Olofsson
f908acc259 Updating docs 
-clarifications
-removing TX DMA
 2015-08-07 09:09:42 -04:00
Andreas Olofsson
7df92eb1f0 Removing DMA from transmit 
* Seems like a useless feature. Why autogenerate the transactions at the transmit side. This should always be done at the receive side to minimize bits moving across the link.  Can't really see a use for it anymore so I am removing it.
* If you want to hack the design to reduce latency, you can always grab the raw etx_core and drive signals directly through write port.
* May consider adding a fourth port to etx to allow bypassing  the link interfac?
* Add an ifdef to bypass the fifos?
 2015-08-07 09:05:11 -04:00
Andreas Olofsson
5e50d78c51 Merge branch 'master' of https://github.com/parallella/oh 2015-08-07 07:56:44 -04:00
Andreas Olofsson
36e8f78370 README changes and various fixes 2015-08-07 07:56:30 -04:00
Andreas Olofsson
cbc029521b Update README.md 2015-08-04 18:08:02 -04:00
Ola Jeppsson
4df38ca35e elink: Update scripts 
Use paths relative top top_srcdir (so scripts can be run from any
directory).
Add missing files
elink_example was renamed to axi_elink?

Fails at placement.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2015-07-05 23:51:19 +02:00
Ola Jeppsson
3db4e49675 elink: Convert package_axi_elink to use helper script 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2015-07-05 19:43:32 +02:00
Andreas Olofsson
9fb9dc1cd5 Adding IP packaging script 2015-07-02 16:58:43 -04:00
Andreas Olofsson
9379484f65 Fifo parameter change 
-Changing parameter name to DW
-Making depth 32 for axi interfaces
(tune this later...)
 2015-07-02 16:55:42 -04:00
Andreas Olofsson
f1b37ab4c4 Ephycard should not be default 2015-07-02 16:54:31 -04:00
Andreas Olofsson
d6f61784b0 Update dv paths 
-includes inside files (methodology change)
-adding ip paths
 2015-07-02 16:48:14 -04:00
Andreas Olofsson
e28cd3cb97 Adding search path for include file 2015-07-02 16:47:07 -04:00
Andreas Olofsson
368836ab9b Adding back a better fufu test vector 2015-07-02 16:46:33 -04:00
Patrik Lindström
a20c9f25ec clean up 2015-07-02 15:01:33 +02:00
Patrik Lindström
4a749bf2d8 timing fixes 2015-07-01 00:14:46 +02:00
Patrik Lindström
6d13611f21 script fixes 2015-06-30 16:02:39 +02:00
Patrik Lindström
667c7cb6a8 script fixes 2015-06-30 14:56:27 +02:00
Patrik Lindström
a284dff462 Bug fixes 2015-06-30 14:04:16 +02:00
Patrik Lindström
634ff371ac Bug fixes 2015-06-30 13:32:05 +02:00
Patrik Lindström
48fdf2d782 Added iostandard parameter 2015-06-30 12:44:22 +02:00
Patrik Lindström
f232d9d297 Changed rx_ref_clk PLL divider 2015-06-30 12:35:38 +02:00
Patrik Lindström
8c0dbffb61 Added different IDW for m_axi and s_axi 2015-06-30 12:31:14 +02:00
Andreas Olofsson
537bb6a330 Cleanup 2015-06-25 22:14:19 -04:00
Andreas Olofsson
e960b6f7c0 Adding IP package reference script 2015-06-25 22:14:05 -04:00
Andreas Olofsson
d9155f6538 Placeholder for elink 2015-06-25 16:17:20 -04:00
Andreas Olofsson
eb7028fdbf Reorg 2015-06-25 16:13:20 -04:00
Andreas Olofsson
badac2aa76 Name changes for signal grouping 2015-06-25 16:09:05 -04:00
Andreas Olofsson
2cbf91b07b Making reset sync in emmu 2015-05-23 22:26:15 -04:00