Andreas Olofsson
65708a2be9
Added wait generator for fifo (experimental)
...
- found it very difficult to get to some of the hard to reach scenarios
- the wait circuit helps generate fifo full
- off by default!
2015-11-24 01:05:04 -05:00
Andreas Olofsson
fa5011937c
Taking away prog_full from wr_en
...
- The point of prog_full is to give us some slack..
2015-11-11 22:32:21 -05:00
Andreas Olofsson
bf614a9873
Cleaning up fifo interface
...
- removing redundant signals
- configuring to put synchronizer inside fifo
- one reset only (not two)
2015-11-09 13:20:46 -05:00
Andreas Olofsson
63bf5d25a4
Moving to active low reset
...
- Because this is the right thing to do for chips
- Not going to tell you why...
2015-11-06 16:51:57 -05:00
Andreas Olofsson
3969e6d19e
Moving to MIT license
2015-11-06 11:25:05 -05:00
Andreas Olofsson
a3b0d9b75c
Fixing pushback bug
...
* Fixed pushback bug at fifo (DUH!)
* Need to verify random pushback at all tx/rx ports
2015-11-02 16:16:10 -05:00
Andreas Olofsson
f42b34ea3c
Moving back to async reset
2015-10-07 19:21:04 -04:00
Andreas Olofsson
d81bb66d73
Writing while full is aserted
2015-08-14 17:15:38 -04:00
Andreas Olofsson
c627827a6b
Fifo cleanup
...
-Adding model (one source..)
-generate for 104x32 for xilinx
-making prog_full the default full indicator
-bringing out almost_full for future use
-fixing interface change in all modules
2015-07-02 16:59:38 -04:00
Andreas Olofsson
1eb2bcea89
Removing custom xilinx primitives
...
-Using the memory_sp macro instead...
-Cleaner design
-axi_elink now works!
2015-05-21 22:54:29 -04:00
Andreas Olofsson
02cc0f2b4f
Adding reset to both sides of fifo
2015-05-14 22:47:25 -04:00
Andreas Olofsson
b2b7f96e86
Making FIFO/memories easier to use
...
-WIDTH/DEPTH parameters
-Removing references to "clean" in ifdefs
2015-05-07 23:50:34 -04:00
Andreas Olofsson
ec3dbc910a
Using async reste on fifo output access signal
...
-For cases where there is no clock at output
2015-05-04 17:07:55 -04:00
Andreas Olofsson
75f653ffd6
Naming cleanup
2015-05-04 10:37:08 -04:00
Andreas Olofsson
19e22c38d7
Adding proper wait to fifo_cdc
...
If there is a waitm, we should
1.) Not increment the read pointer
2.) Hold the packet steady until wait signal goes away
3.) Hold access high, keep request intact
2015-05-03 23:17:23 -04:00
Andreas Olofsson
a58c2d5279
Adding clock domain crossing module for emesh
...
-Generic, built for reuse
2015-05-01 17:13:44 -04:00
