Andreas Olofsson
bf614a9873
Cleaning up fifo interface
...
- removing redundant signals
- configuring to put synchronizer inside fifo
- one reset only (not two)
2015-11-09 13:20:46 -05:00
Andreas Olofsson
3969e6d19e
Moving to MIT license
2015-11-06 11:25:05 -05:00
Andreas Olofsson
1eb2bcea89
Removing custom xilinx primitives
...
-Using the memory_sp macro instead...
-Cleaner design
-axi_elink now works!
2015-05-21 22:54:29 -04:00
Andreas Olofsson
79467583c9
Made reset async (there may not be a clock..)
2015-04-24 17:32:17 -04:00
Andreas Olofsson
e033e233d0
Integrating emesh memory module
...
-This will flush out the final read response path
2015-04-20 23:07:13 -04:00
Andreas Olofsson
7e44dfc84c
Memory read bug (clk floating)
2015-04-19 21:54:22 -04:00
Andreas Olofsson
f606fc5794
Adding high level single ported memory
2015-04-18 16:11:21 -04:00
Andreas Olofsson
b9d3c5ac5c
Verilator lint cleanup
...
~10 real bugs
-mostly name mismatches and bit range mistakes
2015-04-14 14:00:23 -04:00
Andreas Olofsson
d2fc0da3a1
Fixing file permissions
...
Verilog text files should not have execute permissions!
2015-04-08 13:26:12 -04:00
Andreas Olofsson
b0b9315bf1
Massive checkin...
...
-this may break already broken projects
-creates a Verilog top level (instead of using Vivado block level design)
-integrates mmy and mailbox (not completely integrated)
-compiles...
-pours in all of the code from the archive
(some new logic created)
2015-03-24 20:44:03 -04:00
