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957 Commits 7 Branches 1 Tag
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124 Commits

Author SHA1 Message Date
Andreas Olofsson
67afb87881 Cleaning up sp memory changes 
-removing incorrect bist dout port
-repair vector name change
 2016-02-26 17:01:24 -05:00
Andreas Olofsson
d0171fd1d8 Adding ASIC interface to single port memory 
- Yes, I know this means more signals for others to "ignore". The fpga way to handle this is to auto generate hierarchy to hide the signals.
- I prefer a flatter structure with signals tied off and a library of known good components in a repo!
 2016-02-26 16:31:09 -05:00
Andreas Olofsson
5f9fea960a Changing interface for consistency 
-simple functions should strive for "in" and "out" parameters
 2016-02-25 15:02:53 -05:00
Andreas Olofsson
1c0646c569 Implemented absolute value function 2016-02-25 15:00:33 -05:00
Andreas Olofsson
39f8115df8 Adding bitreverse module 2016-02-25 14:50:43 -05:00
Andreas Olofsson
701b1deca3 Bug fix: adding missing event on reset 2016-02-25 14:43:00 -05:00
Andreas Olofsson
4900f2c6e2 Propagating clock during reset 2016-02-25 14:42:39 -05:00
Andreas Olofsson
2a22cd6ff8 Removing delay + clock gating 
- delay could hide bad designs..
- clock gating was hard to handle from outside
 2016-02-25 14:41:30 -05:00
Andreas Olofsson
8f37435d95 Instantiating parallel CRC calculators 2016-02-25 14:40:38 -05:00
Andreas Olofsson
1fa1e05754 Adding parallel CRC generators from @alexforencich 2016-02-25 14:40:02 -05:00
Andreas Olofsson
87848d5a14 Parity operator 2016-02-25 10:56:35 -05:00
Andreas Olofsson
ddfb4e00de Fixing generic fifo 
- This one is looking better
- Still needs more review. At least now it has a testbench...
 2016-02-24 14:26:25 -05:00
Andreas Olofsson
ea2ee15d5c Only run clock divider if enabled 2016-02-24 14:25:53 -05:00
Andreas Olofsson
d246529b4b Fixing sampling bug 2016-02-24 14:25:23 -05:00
Andreas Olofsson
cdef6141b4 Adding 2nd clock to interface 
- Randomizeing clock frequencies
- Phase and frequency randomization a must for catching first order sync problems (and debunking really stupid ideas...)
- Don't be clever, be smart!
 2016-02-24 14:23:30 -05:00
Andreas Olofsson
117a4fee0d Doing forall "dut*.v" 
- Adding entries to a list gets old real fast....
 2016-02-24 14:22:32 -05:00
Andreas Olofsson
fc7dc0e70a Adding "SEED" as basic parameter 
-making randomness clocks a first class citizen
-Verilog doesn't have a seed, need to drive it from the shell
-a must for async clocks, useful for many things
-does not preclude randomization externally as well
 2016-02-24 14:21:04 -05:00
Andreas Olofsson
bb4a602f7f New "dut files" 
- new clocks (clk1 and 2)
- simpler names
- fifo dut
 2016-02-24 14:19:57 -05:00
Andreas Olofsson
c9601a8f9c Adding clk90 output to clkdiv 
-Added testbench
-Needs more review!
 2016-02-23 17:49:08 -05:00
Andreas Olofsson
84490be604 Adding testbench for clockdiv and gray converter 2016-02-23 17:17:41 -05:00
Andreas Olofsson
be22598935 Adding basic unit wiggle tests 2016-02-23 17:17:05 -05:00
Andreas Olofsson
852d7da490 Adding generic target 
- all sims should have a "cfg file"
- since everything is configurable, this is the easiest way
 2016-02-23 15:44:31 -05:00
Andreas Olofsson
5c66c16714 Reorg: moving generic fifo to separate file 
- design was too "xilinx centric" before.
- library should work in any technology
 2016-02-23 15:43:28 -05:00
Andreas Olofsson
91c662e528 Adding experimental fifo circuit 
-not debugged
 2016-02-23 15:42:55 -05:00
Andreas Olofsson
71efa8669f Fixing new ddr circuits 2016-02-23 15:42:32 -05:00
Andreas Olofsson
98a14099ca Fixing basic counter 2016-02-23 15:41:35 -05:00
Andreas Olofsson
8e466f3137 Adding debouncer circuit 2016-02-23 15:41:18 -05:00
Andreas Olofsson
e051d7d516 Adding vectorized iddr/oddr cells 2016-02-22 23:47:27 -05:00
Andreas Olofsson
fd7aff5dd8 Fixing warning messages in chip synthesis tool 
- Don't fight the tools
- No way to remove these warnings and I don't want to have to tell everyone to include maging "don't output this kind of warning flags" that are global to a project...that's just bad practice.
- Didn't take many minutes to remove these warnings and now synthesis runs through with 0 warnings ... much cleaner.. inspires more confidence
 2016-02-12 11:04:52 -05:00
Andreas Olofsson
b516a2cebf Contributing nested interrupt controller 2016-02-11 22:04:36 -05:00
Andreas Olofsson
271e48d3c4 Fixing table formatting issue with logic 2016-02-07 18:09:47 -05:00
Andreas Olofsson
b5f0c775ff Adding constants reference 2016-02-07 18:08:17 -05:00
Andreas Olofsson
e8678bb395 Adding commong docs directory 2016-02-03 23:14:32 -05:00
Andreas Olofsson
c8b9de9f42 Adding gpio and spi paths 2016-01-24 23:42:06 -05:00
Andreas Olofsson
083e459fb0 Fixing issue with empty ip list 2016-01-20 21:46:48 -05:00
Andreas Olofsson
abd25426b6 Fixing various small bugs 
-sandbox accelerator working in simulation!
-t0+6 hrs wall time (lost 2 hours due to travel)
 2016-01-20 17:23:09 -05:00
Andreas Olofsson
b3c0cdc082 Adding generic N:1 mux 2016-01-20 17:22:05 -05:00
Andreas Olofsson
1b6f1ecaef Interface cleanups 2016-01-20 10:51:57 -05:00
Andreas Olofsson
21ac7b690d Adding rd_counter to sync fifo interface 2016-01-20 10:50:00 -05:00
Andreas Olofsson
b26255dfb5 Fixing weird clog2 error in Vivado 
-I guess you can't use built in function with localparam?
 2016-01-19 14:07:04 -05:00
Andreas Olofsson
ca5db9fa4d Interface cleanup 
- fifo interface changes
- maxi/saxi name changes
- general code cleanup
- register remapping for mailbox
 2016-01-19 13:33:08 -05:00
Andreas Olofsson
a270ade1cd Cleaning up FIFO interfaces 
-making sync/async interfaces more uniform
-removing valid signal, useless...
-preparing for count output
 2016-01-19 13:28:47 -05:00
Andreas Olofsson
26a1304405 Fixing silly compiler errors 2016-01-17 21:15:28 -05:00
Andreas Olofsson
a1e19e0a5b Adding time to debug message 
- Very useful, should add these to all muxes!
 2016-01-16 14:43:14 -05:00
Andreas Olofsson
8d6c07be9b Changing timeout 
- Test being cut off too early.
- Really need to implement end of test indication already!!!
 2016-01-13 15:32:15 -05:00
Andreas Olofsson
bed1ba5556 Fixing write to TX register bug 
- The write transaction was incorrectly piped through to axi slave
 2016-01-11 20:50:40 -05:00
Andreas Olofsson
fa42bc6e2e Reset simulation issue 
- Feels like I have seen this before, but still makes me nervous. The async negedge of reset was never being triggered in simulation by iverilog, probably because the simulation initialized it to 0, so there was no negedge. In logic, this is an async level signal....
 2016-01-11 20:47:06 -05:00
Andreas Olofsson
307794711d Error message in one hot mux 2016-01-11 17:35:15 -05:00
Andreas Olofsson
d1062fbff8 Changing dp memory interface in calling module 2016-01-11 17:34:35 -05:00
Andreas Olofsson
d4c5118a72 Making single/dual port memory interfaces constistant 2016-01-11 15:06:22 -05:00