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10 Commits

Author SHA1 Message Date
Andreas Olofsson
b9d3c5ac5c Verilator lint cleanup
~10 real bugs
-mostly name mismatches and bit range mistakes
2015-04-14 14:00:23 -04:00
Andreas Olofsson
bf1671b1e9 Added "fufu" DV environment for elink
-Icarus for now, verilator comes next
-Using our "standard" emesh interface
..here we go...
2015-04-14 11:45:33 -04:00
Andreas Olofsson
084f630c4e Adding missing stubs 2015-04-14 09:42:19 -04:00
Andreas Olofsson
73229ff914 Major cleanup, refactoring, and feature completion
-adding clock bypass mode for esystx[12]
-removing monitor feature on erx
-remove loopback support from doc
-add clock bypass mode for esysclk
-shortening register names (descriptive enough)
-added debug signal information
-moving registers to elink
-making elink version programmable (to support plug in boards)
-reorganized debug signals and added stickys
-added timeout for axi slave
-removed embox status bit (redudant, don't poll status)
-renamed EMBOX0-->EMBOXLO
-moved datain interface straight to ecfg (cleanup)
-changed etx arbiter priority to increase stability
-created the esaxi_mux block
-fixed some missing ports issues in stubs

Now comes the fun part...verification...
Andreas
2015-04-11 00:04:18 -04:00
Andreas Olofsson
239ca128c2 Vivado run through
-missed connections
-mismatched bus widths
-missing IP blocks
-cleanup
-proper DV starts tomorrow
2015-04-08 23:40:16 -04:00
Andreas Olofsson
b0a94d7f43 Adding stubs for IP blocks used in elink 2015-04-08 23:38:36 -04:00
Andreas Olofsson
b0b9315bf1 Massive checkin...
-this may break already broken projects
-creates a Verilog top level (instead of using Vivado block level design)
-integrates mmy and mailbox (not completely integrated)
-compiles...
-pours in all of the code from the archive
(some new logic created)
2015-03-24 20:44:03 -04:00
Fred Huettig
573d322d16 Revert "Fixing port declarations (thanks Verilator!)"
This reverts commit 75310447401bce8561b7a67d4c8aeca27c261464.
2015-01-28 14:15:13 -05:00
aolofsson
2c886c4e24 Fixing port declarations (thanks Verilator!) 2014-12-15 16:39:28 -05:00
aolofsson
47fa7ff23d Adding stubs files for xilinx IP
Goal is to create models for all of these
2014-12-14 22:21:01 -05:00