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Author SHA1 Message Date
Andreas Olofsson
6911b67189 Adding a tapeout checklist 2016-05-31 13:19:26 -04:00
Andreas Olofsson
8b24139be1 Adding ASIC parameter to special library functions 
- Needed to map to specific proprietary libraries
- Need to hide actual cells behind abstraction due to NDA
 2016-04-15 23:25:49 -04:00
Andreas Olofsson
3314051934 Adding delay cell 2016-04-15 23:25:16 -04:00
Andreas Olofsson
a330f73838 Fixing readme 2016-04-15 22:38:06 -04:00
Andreas Olofsson
397b10946f Shortening flow names 
- + reorg
 2016-04-15 22:32:27 -04:00
Andreas Olofsson
09e40875bb Adding wrappers for pnr 2016-04-15 18:01:09 -04:00
Andreas Olofsson
8bfccdfd73 Simplifying synthesis flow 
- Too many steps, some of them were "one line long"
 2016-04-15 17:37:32 -04:00
Andreas Olofsson
53dea826bc Merge branch 'master' of github.com:parallella/oh 2016-04-14 15:55:16 -04:00
Andreas Olofsson
d237c17eba Instantiating generic ram module in dp memory 2016-04-14 15:54:50 -04:00
Andreas Olofsson
f9910d6094 Fixing depth parameter in fifo 2016-04-14 15:54:23 -04:00
Andreas Olofsson
b70b9de811 Merge pull request #65 from olajep/vivado-localparam-clog2-fix 
Vivado doesn't like localparam / clog2 combo
 2016-04-14 15:53:35 -04:00
Andreas Olofsson
305c63c911 Merge pull request #64 from olajep/merge-stable 
Merge stable into master
 2016-04-14 15:53:19 -04:00
Ola Jeppsson
62469afc4b Vivado doesn't like localparam / clog2 combo 
Using parameter instead works.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-14 21:46:14 +02:00
Ola Jeppsson
652f928377 Merge branch 'stable-prepared' into merge-stable 
Conflicts:
      parallella/fpga/headless/Makefile
      parallella/fpga/headless/bit2bin.bif
      parallella/fpga/headless/build.sh
      parallella/fpga/headless/dummy.elf
      parallella/fpga/headless/parallella.bit.bin
      parallella/fpga/headless/run.tcl
      parallella/fpga/sdr_fmcomms/run.tcl
      src/accelerator/fpga/bit2bin.bif
      src/accelerator/fpga/dummy.elf
      src/parallella/dv/build.sh
      src/parallella/fpga/Makefile
      src/parallella/fpga/headless_e16_z7010/Makefile
      src/parallella/fpga/headless_e16_z7010/bit2bin.bif
      src/parallella/fpga/headless_e16_z7010/build.sh
      src/parallella/fpga/headless_e16_z7010/dummy.elf
      src/parallella/fpga/headless_e16_z7010/run.tcl
      src/parallella/fpga/headless_e16_z7020/Makefile
      src/parallella/fpga/headless_e16_z7020/build.sh
      src/parallella/fpga/headless_e16_z7020/parallella.bit.bin
      src/parallella/fpga/headless_e16_z7020/parallella_e16_headless_gpiose_7020.bit.bin
      src/parallella/fpga/headless_e16_z7020/run.tcl
      src/parallella/fpga/sdr_fmcomms/run.tcl

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-14 20:41:47 +02:00
Ola Jeppsson
4c9f3273b1 Move parallella to src/ 
Move parallella to src/ to prepare for merge with master.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-14 20:30:46 +02:00
Ola Jeppsson
8171b9023a src/parallella/fpga: Rename headless to headless_e16_z7020 
Set up paths for merge with stable

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-14 20:26:34 +02:00
Andreas Olofsson
6b72eab0fe Merge pull request #63 from olajep/e16-z7010-headless 
E16 z7010 headless
 2016-04-14 13:52:42 -04:00
Andreas Olofsson
e66c526fec Merge pull request #62 from olajep/gpio-driver 
GPIO: Remove direction cache variable
 2016-04-14 13:00:48 -04:00
Ola Jeppsson
dccfe3d0b4 GPIO: Remove direction cache variable 
Not needed now that GPIO_DIR is readable.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-14 18:57:31 +02:00
Andreas Olofsson
8faa91bc52 Instantiating oh_memory_ram in dp/sp memories 2016-04-14 10:30:19 -04:00
Andreas Olofsson
709f91c306 Using DEPTH as specifier for memory 
- More natural design interface (than AW)
 2016-04-14 10:29:49 -04:00
Andreas Olofsson
a08b5d55b5 Adding generic RAM module 
- one read, one write port
- needed something simpler for modeling, maximuze code reuse
- _sp/_dp are really there so that you can build designs that will abstract away chip/fpga details
 2016-04-14 10:28:30 -04:00
Andreas Olofsson
d730e46e0b Fixing oh_dsync instantiation 
- to add new reset pin (can be tied to 1'b1 sometimes)
 2016-04-13 20:54:12 -04:00
Andreas Olofsson
70340040ce Fixing killer bugs in async fifo! 
- Adding reset on dsync (sometimes there is no clock)
- Separated reset for wr/rd
- One of the sync clocks was wrong (found by review)
 2016-04-13 20:50:48 -04:00
Andreas Olofsson
42c7f4ed0d Improving dsync 
- adding ability to drive random delay values on each bit in multibit sync
- adding async reset (need was found during integration testing)
 2016-04-13 20:48:37 -04:00
Andreas Olofsson
a6e1b22f9f Adding async reset to debuncer. 
- Can't guarantee that there will be a clock at startup.
- All IO modules with suspect clocking situation should have async reset on all key signals.
- To test, then you turn off clock and look for "x propagation".
 2016-04-13 20:47:22 -04:00
Andreas Olofsson
0432f22c67 Simplifyinf bin2gray interface 
- Using gray/bin as inputs was cute, but not useful when actually instantiating and reading the code. in/out works better.
 2016-04-13 20:46:02 -04:00
Andreas Olofsson
3ccd72016e Merge pull request #61 from olajep/gpio-driver 
GPIO driver
 2016-04-13 09:56:37 -04:00
Ola Jeppsson
510b6669a8 GPIO: Add raw register access API 
Add gpio_reg_write() and gpio_reg_read() functions.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-13 15:31:47 +02:00
Ola Jeppsson
137994f13a GPIO: Drop "oh" prefix in file names and API 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-13 15:30:16 +02:00
Andreas Olofsson
ff7018b4ac Making all significant GPIO registers readable for now 
- Would really prefer if this could be handled in the driver..
 2016-04-13 09:02:30 -04:00
Andreas Olofsson
33f3af9f79 Making GPIO_DIR readable 2016-04-13 09:00:24 -04:00
Ola Jeppsson
f22b833908 GPIO: Add GPIO driver 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-13 13:24:29 +02:00
Ola Jeppsson
94b73eb2d0 GPIO: Remove old driver template 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-13 13:17:32 +02:00
Andreas Olofsson
30555c5375 Adding nreset to command reg 
- Not 100% sure on this. Ideally I think you would want the ss signal to be the "reset" of all this logic, but the command register gets too tricky.
- Is there an issue in having a async active low reset pin on the this interface. Considering that this is only a problem for the remote fetch logic (which will definitely have a nreset signal) I think this is ok...
 2016-04-12 09:42:52 -04:00
Andreas Olofsson
24957b73d3 Making interrupt 0 non-maskable. 2016-04-11 20:36:58 -04:00
Andreas Olofsson
e6ed2f2855 Cleanup register addresses of PIC 2016-04-11 20:32:42 -04:00
Andreas Olofsson
6c0ce1ff00 Adding README for PIC 2016-04-11 20:31:30 -04:00
Andreas Olofsson
191f3b4db8 Fixing gpio initial use case example 2016-04-11 19:27:23 -04:00
Andreas Olofsson
7ab30d9f9b Initial thoughts on a gpio driver 2016-04-11 15:46:54 -04:00
Andreas Olofsson
101fb7de66 Copyright transfer 
- All OH! code transferred from Adapteva to non-profit Parallella Foundation
 2016-04-11 12:05:29 -04:00
Andreas Olofsson
1a790eaf24 Preparing for safer clock setting changes 2016-04-11 12:04:30 -04:00
Andreas Olofsson
f25aa0ff45 Cleanup after common lib refactoring 
- clockdiv takes no parameter
 2016-04-11 12:03:44 -04:00
Andreas Olofsson
2688bc5aa4 Refactoring common library 
- Updating interfaces to 2005 style
- Adding license pointers to all files
 2016-04-11 12:01:59 -04:00
Andreas Olofsson
5b8328826e Making rsync interface scalar 
- Who ever uses a vectorized reset....
(if you do, use generate...)
 2016-04-11 11:59:18 -04:00
Andreas Olofsson
fef2bdbe08 Making latch interface generic 
- Should look like a standard cell gate
 2016-04-11 11:58:54 -04:00
Andreas Olofsson
5304fd2df2 Fixing compilation errors 2016-04-11 11:13:08 -04:00
Andreas Olofsson
01a74a3db9 Removing ce from oddr 
- Better to turn off clock if you want to save power
- The CE was actually increasing the power by N x by making every data signal a clock :-)
 2016-04-11 10:30:02 -04:00
Andreas Olofsson
f62d7c0975 Vectorizing csa modules 2016-04-11 09:34:57 -04:00
Andreas Olofsson
d2fbbcf341 Enhancing GPIO block 
- implementing interrupt handling
- edge/level support
- moving to single register for "DIR", avoids confusion
- adding ILATCLR for clearing interrupts
- changing to N parameter away from clumsy 64 bit chunk
- if you want longer GPIO, instantiate more vectors
- up to N==AW supported by this model
- trying out more modern Verilog features
 2016-04-10 23:24:26 -04:00