- Filtering "src" wasn't such a good idea...
- Fixing script for bitstream, bootgen doesn't overwrite existing bit stream files (thanks Xilinx, cost me an hour of anxiety!!)
- reduced frame fanout, removed clock gater in erx_io (improves speed path)
- driving constants on "wid signals" (proper)
- making lock signal 1 bit wide to remove warning
- moved backed to BUFIO for IDDR blocks
-Start with gui
-Generate block design
-Edit text, this is f'ing crazy!
-If this is the only way to use the vivado IP not sure I want it
-Strive towards doing everything in verilog
-Split into:
1.) Verilog block (no IP!)
2.) One top level to instantiate IP + clean verilog block
-Never fight the tools..
