- Very thin file with simulation control specific to simulators
- A similar file needed for Verilator
- The idea is that the testbench can be instantiated in an FPGA/Verilator
- A testbench now continaines a dut, standard stimulus module, and in place logic for checking the result.
- The result checking in verilog is the hardest part and generally not done well.
- For verilator/systemc, we rbing out the checking into software through the interface.
- For simple testing like rng based testing or self checking cpu tests, we add the check in verilog at the testbench level on a per dut basis.
- Better names (clk1/clk2 was confusing)
- Removing supplies (rare special case), handle with ctrl
- Remove sting passing parameters for testname, primitive, not useuful
- Creating an arbitrary 'src' directory really doesn't help much...
- Goal is to make each folder self contained
- Make meta repos and individual repos have the same directory structure
