6 Commits

Author	SHA1	Message	Date
Patrik Lindström	634ff371ac	Bug fixes	2015-06-30 13:32:05 +02:00
Andreas Olofsson	1f6c18a764	Using fifo_cdc instead of fifo_async	2015-05-07 23:45:36 -04:00
Andreas Olofsson	ba32323306	Cleaning up clocks ... -moving to "real" Xilinx PLL instantiation -one PLL for CCLK one for LCLK -removing clock dividers, can't work at speed, put inside model -configuration needs to be done differently -removing pll_bypass signal, can't work with logic -clocks should be done with hard macro primitives (no logic)	2015-05-06 12:23:15 -04:00
Andreas Olofsson	ebd9a89afd	Adding constants to handle model	2015-05-02 21:30:26 -04:00
Andreas Olofsson	8461277ab1	Complete redesign of configuration register file ... -There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect! -Configuration can be done from host through txwr/txrd path of any register -The RX IO pins can only access the RX side of the design	2015-05-01 17:58:16 -04:00
Andreas Olofsson	797d836a02	Renaming constants file	2015-04-22 13:56:48 -04:00