- Making all resets async since we cannot guarantee that we have a clock coming in from RX. This is needed due to the way we use a PLL for alignment. If we would have used a free running local clock this would have been different, but this would have required a FIFO for synchronization betwen the rx and rxdiv4 clock.
- Moving the clock block into the RX for modularity
- Making a specil rx soft reset (driven from sys_clk domain)
- Still there is a POR_reset so the link should wake up ok
-Removing the wait signal from the pipeline
-Assumption is that the prog_full is used on fifo, allowing two entries
to be captured in fifo.
-May revisit this at some time...
-When a read response is detected, there should be no spurious transactions to the RD/WR request fifos.
-Move the "filter" backt to the erx_protocol block
-Removed the remap bypass signal (was hacky)
-Passes simulations again..
The MMU is a monster and may be too much
Adding simple remapping modules
Covers todays feature and then some
1.) Static remapping
2.) Addresss compression
