Andreas Olofsson
6dcd5e96bf
Cleanup after lock width change for zynq axi
2015-11-09 20:39:16 -05:00
Andreas Olofsson
e2c917b6f9
Fixed packet reformatting bug
2015-11-09 20:38:55 -05:00
Andreas Olofsson
497dd71aaa
Fixed readback bug
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- there were hard coded magic number in code, bad practice!
- now works!
2015-11-09 20:38:12 -05:00
Andreas Olofsson
19f773839d
Fixed bug with packet decode
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- mailbox write now working
2015-11-09 20:37:17 -05:00
Andreas Olofsson
13d29f8e67
Stupid typos..
2015-11-09 16:18:20 -05:00
Andreas Olofsson
61eb56c6f7
Final Vivado fixups:
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- reduced frame fanout, removed clock gater in erx_io (improves speed path)
- driving constants on "wid signals" (proper)
- making lock signal 1 bit wide to remove warning
- moved backed to BUFIO for IDDR blocks
2015-11-09 16:09:12 -05:00
Andreas Olofsson
55ba8ff635
Cleaning up warnings from FGPA tools
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- removing unconnected ports
- only one rst input for async_fifo
- synchronizing the reset input toe emaxi fifo
2015-11-09 13:23:40 -05:00
Andreas Olofsson
cf2123ce88
Don't generate fifo during packaging
2015-11-09 13:22:27 -05:00
Andreas Olofsson
c84e1c96b7
Adding hdmi pins for parallella
2015-11-09 13:22:08 -05:00
Andreas Olofsson
64f55eb792
Fix 0 day bug...
...
- this shows why it's so important to read the warnings. (circuit was broken!)
2015-11-09 13:21:26 -05:00
Andreas Olofsson
bf614a9873
Cleaning up fifo interface
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- removing redundant signals
- configuring to put synchronizer inside fifo
- one reset only (not two)
2015-11-09 13:20:46 -05:00
Andreas Olofsson
01fd24e069
Fixing synchronization reset speed path
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- This seems silly, why even have a syncrhonizer
- Safe to set speed path?
2015-11-09 00:16:35 -05:00
Andreas Olofsson
875e4213a5
Adding attributes to sync logic
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- Otherwise tool was throwing away logic and timing incorretly.
- This is why you HAVE to isolate this logic! Solve the problem once for all logic and for everyone.
2015-11-08 23:30:47 -05:00
Andreas Olofsson
3797cac74f
Solving critical paths for TX/RX
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- Using the BUFIO makes another clock domain....FPGAs apparently hate clock domain crossings, avoid them at all cost.
- Now moving back to having on high speed clock domain for logic and DDR blocks, take care of IO alignment in software for TX and RX
- Also, fixed the io_wait path with logic...not sure what I was thinking there. Logic was trivial. The way it was,the io path was going straight into the FIFO as a wait.
2015-11-08 23:28:39 -05:00
Andreas Olofsson
405c322d75
Adding build shell script for headless
2015-11-08 07:33:16 -05:00
Andreas Olofsson
65f772ddef
Fixing careless mistakes..
2015-11-06 22:51:09 -05:00
Andreas Olofsson
9383f32764
Making sure ETYPE is set to 0.
2015-11-06 22:41:43 -05:00
Andreas Olofsson
aa940c2a39
Fixing typos
2015-11-06 22:40:59 -05:00
Andreas Olofsson
b6c95e5b94
Cleanup
2015-11-06 22:34:08 -05:00
Andreas Olofsson
5e18ed8c52
Making defines unique
2015-11-06 22:33:33 -05:00
Andreas Olofsson
979b20a451
Fixing name on fileset for constraints
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- Apparantly has to be fixed to constr&^(I&W)%
2015-11-06 22:32:46 -05:00
Andreas Olofsson
ebf2e861de
Need to validate design before writing tcl
2015-11-06 20:47:35 -05:00
Andreas Olofsson
8b3fa77df1
Added missing index
2015-11-06 20:47:16 -05:00
Andreas Olofsson
1fa3543ba1
Changing back to lower cases, works..
2015-11-06 20:46:41 -05:00
Andreas Olofsson
a683e58597
Associating clock with bus interface
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- This should be moved to the block , block specific...
2015-11-06 20:45:38 -05:00
Andreas Olofsson
6e2ee17481
Updated system memory map
2015-11-06 20:44:18 -05:00
Andreas Olofsson
c9dc9c33ee
Almost done connecting
...
- AXI connections not working properly...
2015-11-06 18:26:09 -05:00
Andreas Olofsson
63bf5d25a4
Moving to active low reset
...
- Because this is the right thing to do for chips
- Not going to tell you why...
2015-11-06 16:51:57 -05:00
Andreas Olofsson
322dc1119c
Adding standard modules for reset and data sync
2015-11-06 16:51:35 -05:00
Andreas Olofsson
8a89b7e185
Adding more structured vivado build files
2015-11-06 14:11:46 -05:00
Andreas Olofsson
84b5af5b3a
Cleanup
2015-11-06 14:10:35 -05:00
Andreas Olofsson
0a110f6e2c
Fixing contribution guidelines
2015-11-06 11:32:53 -05:00
Andreas Olofsson
7fcd0a366f
Adding contribution instructions
2015-11-06 11:31:16 -05:00
Andreas Olofsson
3969e6d19e
Moving to MIT license
2015-11-06 11:25:05 -05:00
Andreas Olofsson
8b2974feae
Massive reorg!
...
- flattening hierarchy
- removing junk
2015-11-06 10:59:22 -05:00
Andreas Olofsson
e47fd56a21
Bulk edits (clean up later)
2015-11-06 07:03:28 -05:00
Andreas Olofsson
d15f67f470
Filtering more Xilinx crud
2015-11-06 07:02:47 -05:00
Andreas Olofsson
22a95292d3
Fixing empty models
2015-11-06 07:02:28 -05:00
Andreas Olofsson
751ad95a16
Adding parallella dir
2015-11-06 07:02:04 -05:00
Andreas Olofsson
0fcea92b0d
Scripts per "project"
2015-11-06 06:58:47 -05:00
Andreas Olofsson
90998b8ad0
Adding parallella synthesis scripts
2015-11-06 06:58:14 -05:00
Andreas Olofsson
6cb5f88073
Moving block deisgns into a single Parallella module
...
- Easier to maintain
- Better sandbox
2015-11-06 06:56:56 -05:00
Andreas Olofsson
5086052cb5
Adding timing constraints
...
- structure feels right
- one folder per reusable module
- everything should be contained within one "package"
2015-11-04 22:13:35 -05:00
Andreas Olofsson
81fe46a929
Removing xpr file
...
(everything done through tcl)
2015-11-04 22:12:50 -05:00
Andreas Olofsson
025af1ee54
Yay! Now runs to completion
2015-11-04 22:11:19 -05:00
Andreas Olofsson
ee6a9a93ac
Updating scripts
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- adding more compatibility families
2015-11-04 21:46:15 -05:00
Andreas Olofsson
92272e211d
Adding missind dirs in comamnd file
2015-11-04 20:04:44 -05:00
Andreas Olofsson
6a423b5999
Improcing mmcm/pll clock path
...
-apparantly the BUFG in the feedback was not liked by the P&R
2015-11-04 20:02:45 -05:00
Andreas Olofsson
49bf52374d
Changing model to use parameter rather than tick-define
2015-11-04 20:01:31 -05:00
Andreas Olofsson
2ed60c5698
Merge branch 'master' of https://github.com/parallella/oh
2015-11-04 19:20:13 -05:00
