Andreas Olofsson
6dcd5e96bf
Cleanup after lock width change for zynq axi
2015-11-09 20:39:16 -05:00
Andreas Olofsson
e2c917b6f9
Fixed packet reformatting bug
2015-11-09 20:38:55 -05:00
Andreas Olofsson
497dd71aaa
Fixed readback bug
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- there were hard coded magic number in code, bad practice!
- now works!
2015-11-09 20:38:12 -05:00
Andreas Olofsson
13d29f8e67
Stupid typos..
2015-11-09 16:18:20 -05:00
Andreas Olofsson
61eb56c6f7
Final Vivado fixups:
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- reduced frame fanout, removed clock gater in erx_io (improves speed path)
- driving constants on "wid signals" (proper)
- making lock signal 1 bit wide to remove warning
- moved backed to BUFIO for IDDR blocks
2015-11-09 16:09:12 -05:00
Andreas Olofsson
55ba8ff635
Cleaning up warnings from FGPA tools
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- removing unconnected ports
- only one rst input for async_fifo
- synchronizing the reset input toe emaxi fifo
2015-11-09 13:23:40 -05:00
Andreas Olofsson
bf614a9873
Cleaning up fifo interface
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- removing redundant signals
- configuring to put synchronizer inside fifo
- one reset only (not two)
2015-11-09 13:20:46 -05:00
Andreas Olofsson
01fd24e069
Fixing synchronization reset speed path
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- This seems silly, why even have a syncrhonizer
- Safe to set speed path?
2015-11-09 00:16:35 -05:00
Andreas Olofsson
3797cac74f
Solving critical paths for TX/RX
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- Using the BUFIO makes another clock domain....FPGAs apparently hate clock domain crossings, avoid them at all cost.
- Now moving back to having on high speed clock domain for logic and DDR blocks, take care of IO alignment in software for TX and RX
- Also, fixed the io_wait path with logic...not sure what I was thinking there. Logic was trivial. The way it was,the io path was going straight into the FIFO as a wait.
2015-11-08 23:28:39 -05:00
Andreas Olofsson
65f772ddef
Fixing careless mistakes..
2015-11-06 22:51:09 -05:00
Andreas Olofsson
9383f32764
Making sure ETYPE is set to 0.
2015-11-06 22:41:43 -05:00
Andreas Olofsson
b6c95e5b94
Cleanup
2015-11-06 22:34:08 -05:00
Andreas Olofsson
5e18ed8c52
Making defines unique
2015-11-06 22:33:33 -05:00
Andreas Olofsson
63bf5d25a4
Moving to active low reset
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- Because this is the right thing to do for chips
- Not going to tell you why...
2015-11-06 16:51:57 -05:00
Andreas Olofsson
3969e6d19e
Moving to MIT license
2015-11-06 11:25:05 -05:00
Andreas Olofsson
8b2974feae
Massive reorg!
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- flattening hierarchy
- removing junk
2015-11-06 10:59:22 -05:00
Andreas Olofsson
e47fd56a21
Bulk edits (clean up later)
2015-11-06 07:03:28 -05:00
Andreas Olofsson
5086052cb5
Adding timing constraints
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- structure feels right
- one folder per reusable module
- everything should be contained within one "package"
2015-11-04 22:13:35 -05:00
Andreas Olofsson
81fe46a929
Removing xpr file
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(everything done through tcl)
2015-11-04 22:12:50 -05:00
Andreas Olofsson
025af1ee54
Yay! Now runs to completion
2015-11-04 22:11:19 -05:00
Andreas Olofsson
ee6a9a93ac
Updating scripts
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- adding more compatibility families
2015-11-04 21:46:15 -05:00
Andreas Olofsson
92272e211d
Adding missind dirs in comamnd file
2015-11-04 20:04:44 -05:00
Andreas Olofsson
6a423b5999
Improcing mmcm/pll clock path
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-apparantly the BUFG in the feedback was not liked by the P&R
2015-11-04 20:02:45 -05:00
Andreas Olofsson
8938c396b6
Merge pull request #15 from peteasa/packagingPathUpdates
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Updated paths and added missing source
2015-11-04 17:57:49 -05:00
Andreas Olofsson
30077cc1e5
Scripted elink build script (version 0)
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- starting to feel better about structure
2015-11-04 17:53:54 -05:00
Peter Saunderson
9009113162
Updated paths and added missing source
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Signed-off-by: Peter Saunderson <peteasa@gmail.com>
2015-11-04 20:14:57 +00:00
Andreas Olofsson
6b83cdb0d7
Testbench bug fix
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- can't connect a 64 bit interface to a 32bit one...
- (abuse of emaxi..)
2015-11-03 21:50:26 -05:00
Andreas Olofsson
f849f2410f
Adding infrastructure for axi_elink
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- Need to clean up some of these files later
2015-11-03 19:52:08 -05:00
Andreas Olofsson
36b0f14ca5
"Fixing" wait signal
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- Giving a wait on every ack just doesn't make sense on the read port with a fifo there??
- Makes for a nasty combinatorial loop during integration.
- Test passes (but need to look into this more)
2015-11-03 19:49:38 -05:00
Andreas Olofsson
6114471935
Adding active signal to interface
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- kind of like "pll lock"
2015-11-03 19:49:09 -05:00
Andreas Olofsson
b4daf73157
Optimizing clock path
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* Sven's help!
* Better to use bufio to keep all paths internal, more determenistic path
2015-11-03 14:15:09 -05:00
Andreas Olofsson
fb45666b13
Adding idelay config register documentation
2015-11-03 10:46:05 -05:00
Andreas Olofsson
d7bf1389d6
Changing idelay bit map
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- the 5 bit fields was driving me nuts!
- always work in nibbles, place the msb elsewhere (or work with 16 bit values)
2015-11-03 10:31:06 -05:00
Andreas Olofsson
275ed5252f
Adding test for sweeping idelay and testing reads
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-It works!!!!
2015-11-03 10:30:20 -05:00
Andreas Olofsson
971b591454
Shifting first byte of packet down by one bit to accomodate new format
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- this of for future proofing
2015-11-02 20:51:35 -05:00
Andreas Olofsson
02b22a36f3
Fixing test to conform to new stimulus format
2015-11-02 20:51:03 -05:00
Andreas Olofsson
2b67e0007a
Updated simulation instructions
2015-11-02 19:28:00 -05:00
Andreas Olofsson
96abfe3105
Initial register test (still debugging)
2015-11-02 19:27:41 -05:00
Andreas Olofsson
983c4db449
Link cleanup
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- Using new packet interface
- Adding active signal, indicating that link is ready. This way you don't need to guess when the link is ready (no magic constants)
- Removed register on por reset input to get rid of x on startup.
2015-11-02 16:10:05 -05:00
Andreas Olofsson
ec9c3d9e44
Delete old files
2015-11-02 16:08:14 -05:00
Andreas Olofsson
34d379ecb9
Adding new "simpler" test infrastruture
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- build elink with one command
- place all tests in tests/ directory
- new stimulus format followed
- dut_elink.v created
2015-11-02 16:04:46 -05:00
Andreas Olofsson
581c2943f5
Fixing pushback bug in emmu
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- reset was broken!
- need to account for wait
- merging read/write wait for simplicity, otherwise you would need to reset the packets to figure out if it's a read or write transaction...and I don't want to reset every packet throughout the pipe.
2015-10-19 11:08:28 -04:00
Andreas Olofsson
b19f04cfd7
Updating clocking documentation
2015-10-08 10:45:43 -04:00
Andreas Olofsson
d275406aa6
Reset timing optimization
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- holding rx in reset state until tx is done
- removing reset from all pipeline registers
- removing reset from oddr/iddr
- the idea is to keep things quiet not to block in lots of places. The only real block needed is in the FIFO to keep "noise" from propagating past the link. The link should be kept in a safe reset state until the rx fram is stable and the clock is running so that the pipe can be cleaned out.
2015-10-08 10:34:59 -04:00
Andreas Olofsson
6d2b3d63fe
Improving sys_reset timing
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- removing pass through path
- registering sys_reset input
2015-10-08 10:33:38 -04:00
Andreas Olofsson
86e8579e48
Adding testmode for RX
2015-10-07 21:58:50 -04:00
Andreas Olofsson
e1f17b2fa1
Fixing PLL feedback path
2015-10-07 21:58:30 -04:00
Andreas Olofsson
d7ba590250
Changing back to sync for iddr
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-not sure what to do here!!!
2015-10-07 21:58:06 -04:00
Andreas Olofsson
cd597cd5b1
Fixing RX reset (again!)
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-async assert
-sync deassert
2015-10-07 20:37:49 -04:00
Andreas Olofsson
ccad681b0e
Fixing testbench for new clocks
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- Yay! Lots of logic removed
- elink passes again!!!
2015-10-07 19:21:36 -04:00
