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Commit Graph

Author	SHA1	Message	Date
Andreas Olofsson	710c48b880	Fixed clock divider circuit -changed ecfg clock default values, elink default is now the PLL clock/128 coming out of reset -should work in any implementation? -still have to implement the Xilinx specific stuff	2015-04-15 14:56:29 -04:00
Andreas Olofsson	69f3df4140	Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)	2015-04-15 11:54:43 -04:00

Author

SHA1

Message

Date

Andreas Olofsson

710c48b880

Fixed clock divider circuit

-changed ecfg clock default values, elink default is now the PLL clock/128 coming out of reset
-should work in any implementation?
-still have to implement the Xilinx specific stuff

2015-04-15 14:56:29 -04:00

Andreas Olofsson

69f3df4140

Continued work to create clean design:

-pll bypass for clocks (customer request)
-adding dividers on all clocks (tx/cclk)
-adding reset block (clearer)
-using commong clock_divider block
-need to clean up divider block later today, slightly broken:-)

2015-04-15 11:54:43 -04:00

2 Commits