Andreas Olofsson
b0b9315bf1
Massive checkin...
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-this may break already broken projects
-creates a Verilog top level (instead of using Vivado block level design)
-integrates mmy and mailbox (not completely integrated)
-compiles...
-pours in all of the code from the archive
(some new logic created)
2015-03-24 20:44:03 -04:00
Andreas Olofsson
0aa949b382
Fixing typo
2015-03-23 15:46:56 -04:00
aolofsson
1346c02803
Verilator inspired bug fixes
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-address width in elink
-bus widths in ecfg
-command file more generic
2014-12-15 15:25:09 -05:00
aolofsson
7b6b281862
Adding new elink top level file written in verilog.
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Compiles and runs (needs work)
2014-12-14 22:19:02 -05:00
aolofsson
0cd5939a26
Adding fofo environment for elink to check for broken signals.
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Too many stub modules to be practical..next need sim models
2014-12-14 22:17:23 -05:00
aolofsson
d2a4d1431b
Moving file to elink (makes more sense):
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Each directory should be a self contained "object"
2014-12-14 17:41:07 -05:00
aolofsson
c9a70e5f6b
An unverified clean top level elink design module
2014-12-14 17:25:46 -05:00
aolofsson
94ef357c52
Removing old files not needed by new design
2014-12-12 12:27:22 -05:00
aolofsson
6778fce054
Cleaning up old files..
2014-11-06 15:40:40 -05:00
aolofsson
b151bc90e1
More file organization
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Adding some more utility functions
2014-11-06 12:19:39 -05:00
aolofsson
60182e52e3
A "complete" elink top level block with all new features added. Still need
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to work on the axi side.
2014-11-06 12:18:16 -05:00
aolofsson
3f513c9d84
Basic interfaces..still need to add the axi signals and fill in the content
2014-11-06 12:16:09 -05:00
