Andreas Olofsson
71b467728d
Making mux parametrized
2015-12-07 11:19:12 -05:00
Andreas Olofsson
19fa611bb9
Massive reorganization to impove reuse
...
- adding more chip code
- pushing memory stuff into common
- making common "oh_" naming class
-
2015-11-30 13:45:49 -05:00
Andreas Olofsson
847eae23ab
Adding proper read alignment for ememory model
...
-Byte/shorts now work
2015-11-12 10:49:40 -05:00
Andreas Olofsson
3969e6d19e
Moving to MIT license
2015-11-06 11:25:05 -05:00
Andreas Olofsson
e47fd56a21
Bulk edits (clean up later)
2015-11-06 07:03:28 -05:00
Andreas Olofsson
6d9d9702d8
Simulation file cleanup
2015-11-03 19:53:43 -05:00
Andreas Olofsson
46687fe7fd
New packet format
...
* Removed acess at bit [0], was redundant...
* Frees up one more bit for ctrlmode
2015-11-02 20:52:27 -05:00
Andreas Olofsson
22714f3d9d
Adding new emesh format files
...
* Adding an improved monitor file
* Adding mesh interface (avoids crud logic at top level)
* A emesh packet memory module
2015-11-02 16:14:08 -05:00
Andreas Olofsson
c627827a6b
Fifo cleanup
...
-Adding model (one source..)
-generate for 104x32 for xilinx
-making prog_full the default full indicator
-bringing out almost_full for future use
-fixing interface change in all modules
2015-07-02 16:59:38 -04:00
Andreas Olofsson
bba7511f15
Fixing syntax errors caught in synthesis
2015-05-06 12:27:13 -04:00
Andreas Olofsson
a36875ac09
Adding basic emehs transaction generator
...
-Replace with DMA...
2015-05-05 21:39:20 -04:00
