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Author SHA1 Message Date
Ola Jeppsson
74eb5be55b zcu102: Add some documentation 
- Carrier board FMC pinout.
- ZCU102 master XDC file.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 17:54:58 +01:00
Ola Jeppsson
d7fee44574 zcu102: Fix constraints 
- Some pin mappings were wrong (don't code when tired).
- Use 1.8v IO standards.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 17:52:12 +01:00
Ola Jeppsson
06e80284b2 zcu102: Add constraints for SI570 video clock 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 17:51:42 +01:00
Ola Jeppsson
049a031e47 common/hdl: Fix syntax error when CFG_ASIC is undefined 
Workaround for:
Recent Vivado (2016.4) synth step seems to have dropped support for
"-verilog_define CFG_ASIC=0"

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-03 02:26:37 +01:00
Ola Jeppsson
6a50842b46 zcu102: Update block design 
Ports:
Remove HDMI ports.
Remove cclk0 port.
Add cclk0_[pn] (tile 0-7) ports.
Add cclk1_[pn] (tile 8-15) port.
Add clkpd_1p8v port.

Nets:
Connect zcu102_base/cclk to cclk0 and cclk1.
Connect clkpd_1p8v to zcu102_base_0/chip_nreset.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-03 00:53:47 +01:00
Ola Jeppsson
094f417f66 zcu102: Add package pins for FMC0 connector 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-03 00:47:18 +01:00
Ola Jeppsson
bac760678c Add zcu102 design 
Work in progress.
Design looks good.
Need to add pin and timing constraints.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-01 11:11:37 +01:00
Ola Jeppsson
440005fbc0 common/fpga/create_ip.tcl: Add Ultrascale+ to supported families 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-01-31 18:49:12 +01:00
Ola Jeppsson
12e7b5ad14 ip: fifo_async_104x32: Switch to ultrascale device 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-01-31 18:42:47 +01:00
Ola Jeppsson
83a37d2469 ip: fifo_async_104x32: Update to Vivado 2016.4 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-01-31 13:42:59 +01:00
Andreas Olofsson
e7abddbcb5 Adding planning document for boards 
-Not CAD accurate, only for visual planning
 2016-12-21 12:05:37 -05:00
Andreas Olofsson
b350deb827 Adding directory of standards 
-Summary
 2016-11-15 06:51:39 -05:00
Andreas Olofsson
d1f9bdffbb Adding place holder definition for open source 2016-10-24 11:24:08 -04:00
Andreas Olofsson
63f77ef832 Format change for board record 
- explicit link
- adding docs
 2016-10-24 11:17:45 -04:00
Andreas Olofsson
8e195c4d17 Cleanup 2016-10-24 10:57:24 -04:00
Andreas Olofsson
6546787c77 Adding Rascal board 2016-10-24 10:52:24 -04:00
Andreas Olofsson
e7745a3bec Link cleanup 2016-10-24 10:33:30 -04:00
Andreas Olofsson
3ac57dabba Adding open source board resource 2016-10-24 10:27:58 -04:00
Andreas Olofsson
383cda2550 Adding preliminary r5 opcodes 2016-09-26 15:16:00 -04:00
Andreas Olofsson
5a583c598c Adding buffer 
- Sometimes you need to instatiate buffers manually in RTL to get around some absolutely braindead behaviour in eda tools. Not often, but sometimes...
 2016-09-03 14:59:30 -04:00
Andreas Olofsson
70533b57b0 Refactoring asic code 
- remove redundant hierarchy
- using shorter/better names to make sdc constraints less ugly
 2016-09-03 14:40:51 -04:00
Andreas Olofsson
94469ed5f4 Resetting shift register 
- Less red to look at...
 2016-09-03 14:40:21 -04:00
Andreas Olofsson
a306aa5178 Removing one level on redirection on clockor 
- It was getting annoying....
 2016-09-02 00:39:32 -04:00
Andreas Olofsson
128c4015b3 Adding reset to wakeup pipeline 
- Suspect behaviour when clock is absent..
 2016-09-01 19:32:48 -04:00
Andreas Olofsson
0f8beea513 Fixing reset bug for MIO emode 
- Shows up when there is no free running clock. Don't assume there is a clock at startup!
 2016-08-28 19:14:45 -04:00
Andreas Olofsson
3e18d921d6 Adding DV hook into SPI block 
- Inputting large amount of data through SPI in DV is soooo painfully slow. Added hook to speed up development. 100x speedup in verification time-->100x speed up in design team.
 2016-08-26 23:50:05 -04:00
Andreas Olofsson
dc22df0d5c Fixing MIO synthesis errors/warnings 2016-08-26 00:41:42 -04:00
Andreas Olofsson
a13b665027 SPI synthesis cleanup 2016-08-26 00:40:09 -04:00
Andreas Olofsson
ac735cba6a Fixing MIO emesh transaction bug 
- data should go straight into fifo for first cycle
- after that, the data is taken from a temporary buffer
 2016-08-25 21:01:44 -04:00
Andreas Olofsson
073d003e40 Fixing MIO transmit DDR mode 
-iowidth refers to the size of a single ended bus
-DDR is implicitly half that size
 2016-08-25 21:01:01 -04:00
Andreas Olofsson
ebeeb1dd8b Fixing bug in MIO receiver 
-nibble wide io now supported in RX
 2016-08-25 21:00:34 -04:00
Andreas Olofsson
c566f46a60 Adding missing parameter in MIO 2016-08-25 17:53:02 -04:00
Andreas Olofsson
988d4dbd94 Fixing MIO mode switch bug 
- Need to look over this circuit again, feels nasty. There is a ever rotating state here, that should probably be reset when there is no transaction, but how?
 2016-08-25 17:29:55 -04:00
Andreas Olofsson
a65bfafbb6 Fixing MIO DDR mode 
Works!
 2016-08-25 17:29:29 -04:00
Andreas Olofsson
ae8264afc1 MIO interface changes cleanup 2016-08-25 15:43:55 -04:00
Andreas Olofsson
c9046cd645 Implementing amode/emode receiver 
-emode debugged, working!!
 2016-08-25 15:43:27 -04:00
Andreas Olofsson
ae24a4754c Changing to datamode in rx 
- More standard
 2016-08-25 15:42:48 -04:00
Andreas Olofsson
97ef662e38 Fixing various simple MIO receiver IO bugs 
- Really a nice reverse of TX logic...
- Support for partially full transfers when frame goes low
 2016-08-25 14:15:40 -04:00
Andreas Olofsson
401b0a64f9 Connecting missing clock 2016-08-25 14:15:25 -04:00
Andreas Olofsson
5ee15b4802 Fixing default config for new register file 2016-08-25 12:40:29 -04:00
Andreas Olofsson
75267a539e Fixing bugs in transmit logic 
- Serializer wait was missing
- Need to reload on last cycle before emptying to avoid stall, need "next"
 2016-08-25 12:39:16 -04:00
Andreas Olofsson
e36519138a Adding extra cycle to make number of bytes even 
- Needed for ddr operation
- Enables IOW=16 for sdr mode
 2016-08-25 12:38:34 -04:00
Andreas Olofsson
ac90486cb1 New MIO interface 
- Work in progress, compiles but not yet debugged
 2016-08-25 11:57:28 -04:00
Andreas Olofsson
f560a5fc20 Adding iowidth as dynamic parameter for MIO 2016-08-25 11:56:42 -04:00
Andreas Olofsson
f6cb0bb7bf Redesigning MIO rx 
- Standardize on 64bit FIFO interface
- Stuff bytes into shifter register before transferring to fifo
- Use valid bits per byte to keep track of valid data through pipe
- Work in progress...
 2016-08-25 11:55:06 -04:00
Andreas Olofsson
1b24fabe15 Adding missing wait signal to rx 2016-08-25 11:54:54 -04:00
Andreas Olofsson
9919a34c44 Adding iowidth as parameter to MIO 2016-08-25 11:54:36 -04:00
Andreas Olofsson
9e7e771898 Fixing non-blocking bug in dv 2016-08-25 11:45:20 -04:00
Andreas Olofsson
bfb03e31b3 Fefactoring to clarify register usage 2016-08-25 11:44:30 -04:00
Andreas Olofsson
4354a46dce Adding new fifos for MIO 
-In preparation for redesign
 2016-08-25 11:43:48 -04:00