Andreas Olofsson
b25ad633f7
Readback cleanup
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RX/TX interfaces should be mininmized and standalone
Adding mux to consolidate to one "dout"
2015-04-24 17:27:35 -04:00
Andreas Olofsson
3b637e55f0
MILESTONE: Design once again passes test
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New features:
DMA
MAILBOX directly in RX path
TXMMU
2015-04-23 23:16:03 -04:00
Andreas Olofsson
0ed6afeac9
Added tag and group for read response
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-Still not sure about this..
2015-04-23 23:14:39 -04:00
Andreas Olofsson
46896c63ef
Bug fix, adding reset signal
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This will blocking when there is no clock at startup.
2015-04-23 23:13:05 -04:00
Andreas Olofsson
24fc91072d
Adding IDs to keep access signals straight
2015-04-23 23:11:58 -04:00
Andreas Olofsson
01fec0f72a
Fixed elink missind ID parameter
2015-04-23 20:07:52 -04:00
Andreas Olofsson
5c8fb41849
Fifo read bug
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-fifo should be read when it's not empty and there is no wait pushback
2015-04-23 20:07:10 -04:00
Andreas Olofsson
c4c1edc10f
Adding reset to critical signals in pipe
2015-04-23 20:06:11 -04:00
Andreas Olofsson
7ab3b3a8f8
Fixed floating net bug
2015-04-23 20:05:00 -04:00
Andreas Olofsson
0f0ff55928
Verilator based lint cleanup
2015-04-23 18:57:55 -04:00
Andreas Olofsson
155f6a9401
File cleanup
2015-04-23 18:10:07 -04:00
Andreas Olofsson
842dd60b3e
Adding DMA register to regmap
2015-04-23 18:08:52 -04:00
Andreas Olofsson
c76bce1ea3
Changing so basic elink unti is without AXI
2015-04-23 18:08:20 -04:00
Andreas Olofsson
fcf5bf010f
Splitting register file into separate pieces
2015-04-23 18:07:50 -04:00
Andreas Olofsson
ec0c9ce835
Changing to packet interface
2015-04-23 18:07:27 -04:00
Andreas Olofsson
ed0b8c2539
Major RX change:
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-renamed interfaces to rxwr,rxrd,rxrr (much simpler to remember for me)
-packet interface change
-removed wait signals from dataout field
-added dma, emmu, mailbox, config register
-instantiating fifo_sync raw (without wrapper)
2015-04-23 18:04:39 -04:00
Andreas Olofsson
2707541eab
Adding DMA source and changing interface
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-DMA added as a master driving out transactions
(this is going to be great!!)
-Changing to packet interface
2015-04-23 18:03:10 -04:00
Andreas Olofsson
842a6d894a
Fixing enable/reset:
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-Removing enable from ISERDES, not healthy
-Moving all logic to protocol block. (this is an IO block)
-Removing tow redundant pipeline stages (check this??)
2015-04-23 18:01:19 -04:00
Andreas Olofsson
7418d45f5e
Cleanup
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-Packet interface change
-Adding RX enable logic with synchronizer (better place than erx_io)
2015-04-23 17:59:36 -04:00
Andreas Olofsson
d9525b6ae4
Major upgrade
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-Adding DMA, EMMU, CFG
-Removing redundant signals
-Changing to packet interface
2015-04-23 17:58:18 -04:00
Andreas Olofsson
9a614d1094
Packet interface change
2015-04-23 17:57:24 -04:00
Andreas Olofsson
44f162ec09
Packet interface change
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-Changed packet interface
-Removed rd/wr from block, was pass through
2015-04-23 17:56:15 -04:00
Andreas Olofsson
1e1644138e
Splitting register file (rx,tx,base)
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The goal is to have 100% independence in RX and TX pipes
2015-04-23 17:50:45 -04:00
Andreas Olofsson
cc5f165454
Clarified lclk names
2015-04-22 15:03:24 -04:00
Andreas Olofsson
703da8445b
deleted junk
2015-04-22 15:02:31 -04:00
Andreas Olofsson
797d836a02
Renaming constants file
2015-04-22 13:56:48 -04:00
Andreas Olofsson
275264c84d
Reorg
2015-04-21 21:33:49 -04:00
Andreas Olofsson
035b3c9ba5
Milestone: WRITE AND READ FROM HOST WORKS!
2015-04-21 17:16:20 -04:00
Andreas Olofsson
d0b04687ea
Bug fix, missing pipeline stage on read response
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-Apparantly old FIFO was not pipelined (IE data comes back same cycle).
-Not knowing the Xilinx logic, I made it a regular one cycle pipeline
memory based FIFO
2015-04-21 17:14:30 -04:00
Andreas Olofsson
0d42736914
Implemented enesh memory
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-not parametrized
-keeping 64 bit wide for now
2015-04-21 17:13:09 -04:00
Andreas Olofsson
2369e92ffa
Bug fix, missing "data hold" stage
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Hadn't realized that the data needed to be held
Need to look at this logic again!
For now going back to old logic
2015-04-21 17:10:51 -04:00
Andreas Olofsson
e033e233d0
Integrating emesh memory module
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-This will flush out the final read response path
2015-04-20 23:07:13 -04:00
Andreas Olofsson
4c44c59079
Message box working...
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-More testing needed!
2015-04-19 21:55:07 -04:00
Andreas Olofsson
7c93c565e9
Adding back awid, arid, lock to AXI interface
2015-04-18 17:35:22 -04:00
Andreas Olofsson
9e931c47ec
Cleanup
2015-04-18 16:26:32 -04:00
Andreas Olofsson
f141a0e320
Clock cleanup
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-Adding enable signal to clock out. Definitely right decision to keep
separate bit from the divider field.
-Fixed settings for to fit new register field
-XILINX version is still broken!!
2015-04-18 16:24:26 -04:00
Andreas Olofsson
b30dbe6005
Fixed to fit with new register map
2015-04-18 16:23:35 -04:00
Andreas Olofsson
00a921b839
Changed register map
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-Moved "groups" to E,D,C
-Changed names to EL* (shorter is better, clear enough)
-Moved order to fit logical operation during init
-Moved embox registers to MMR group
DONE!
2015-04-18 16:21:45 -04:00
Andreas Olofsson
27087fb736
ESAXI cleanup
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-widen address bus to 32 bits
-blocking access to elink on ecfg access
-fixing decoding for embox
2015-04-18 16:18:41 -04:00
Andreas Olofsson
baf6cc5a62
Removed synchronizer on TXLCLK
2015-04-18 16:17:44 -04:00
Andreas Olofsson
85db5d9de0
Spell checking comments
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First time ever using spell cheker in EMACS. Hard to believe...but it's true!
I am sure this speaks volume for how little I have commented my code over the years!
2015-04-18 06:36:33 -04:00
Andreas Olofsson
c41a0a8640
Cleaning up licenses for consistency
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-All files still GPLv3
-Placed at the bottom of the file (I am tired of looking at them!)
2015-04-17 22:21:08 -04:00
Andreas Olofsson
18b2c489b0
Adding documentation to elink top level module
2015-04-17 22:10:14 -04:00
Andreas Olofsson
08a31cd971
MILESTONE: Open souce simulation elink loopback working!
2015-04-17 15:51:55 -04:00
Andreas Olofsson
bd90cc8f92
Fixed testbench bug (copy paste, RX not enabled)...
2015-04-17 10:08:17 -04:00
Andreas Olofsson
068d63279b
Changing ESYSCLK definition (again.....)
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old implementation felt too "cutsy"
this makes for a cleaner usage model (simple shift with param)
also splitting out enable but, not making the CTIMER mistake again
2015-04-16 22:31:36 -04:00
Andreas Olofsson
dcdf4a9231
Adding experimental OSERDESE2 model
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Experimental model, dirty design
Bits are coming out and frame looks good..
Will continue with RX and debugging tomorrow
2015-04-15 23:03:33 -04:00
Andreas Olofsson
bdec6c1067
Cleaning up tx config register
2015-04-15 17:53:50 -04:00
Andreas Olofsson
846bfa3357
Fixing startup issues in transmit path:
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-adding reset signals to synchronizer to solve startup issues
-setting config in test bench for speedup, default reg config now correct
-fix (my) stupid bug in etx_arbiter
-adding reset to fifo (todo: review this!)
-reviewing "all red" from waveforms is a must. Red (x) on data is ok, but leaving them on control signals is asking for trouble. Better safe than sorry when it comes to reset.
2015-04-15 16:33:20 -04:00
Andreas Olofsson
710c48b880
Fixed clock divider circuit
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-changed ecfg clock default values, elink default is now the PLL clock/128 coming out of reset
-should work in any implementation?
-still have to implement the Xilinx specific stuff
2015-04-15 14:56:29 -04:00
