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120 Commits 7 Branches 1 Tag
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3 Commits

Author SHA1 Message Date
Andreas Olofsson
b1a9f502ca Xilinx models 
-adding ODDR model
-configuring the ecfg (rx/tx/clk) in testbench
 2015-04-15 17:54:19 -04:00
Andreas Olofsson
239ca128c2 Vivado run through 
-missed connections
-mismatched bus widths
-missing IP blocks
-cleanup
-proper DV starts tomorrow
 2015-04-08 23:40:16 -04:00
aolofsson
47fa7ff23d Adding stubs files for xilinx IP 
Goal is to create models for all of these
 2014-12-14 22:21:01 -05:00