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Author SHA1 Message Date
aolofsson
2cb3b9a29b Consolidating all axi interface in one directory 
Adding interface for axi lite slave, needs content
 2014-12-14 22:22:49 -05:00
aolofsson
47fa7ff23d Adding stubs files for xilinx IP 
Goal is to create models for all of these
 2014-12-14 22:21:01 -05:00
aolofsson
7b6b281862 Adding new elink top level file written in verilog. 
Compiles and runs (needs work)
 2014-12-14 22:19:02 -05:00
aolofsson
0cd5939a26 Adding fofo environment for elink to check for broken signals. 
Too many stub modules to be practical..next need sim models
 2014-12-14 22:17:23 -05:00
aolofsson
d2a4d1431b Moving file to elink (makes more sense): 
Each directory should be a self contained "object"
 2014-12-14 17:41:07 -05:00
aolofsson
c9a70e5f6b An unverified clean top level elink design module 2014-12-14 17:25:46 -05:00
aolofsson
4f51cc342d Adding new verilog modules for receiver and transmitter 
-moving away from Vivado block editor
-creating a "clean" split between RX and TX
 2014-12-14 17:18:53 -05:00
aolofsson
4944fa321a Adding axi lite interface to be used by various registers 2014-12-14 17:17:04 -05:00
aolofsson
6dd3c27936 Incremental renaming 2014-12-14 09:14:25 -05:00
aolofsson
c2476e4a33 Created a verilog wrapper for the elink transmitter 
(moving away from the Vivado block editor)
 2014-12-12 20:36:15 -05:00
aolofsson
f8bbb289ff Changed module name for new structure 2014-12-12 16:35:59 -05:00
aolofsson
100e17a304 Renamed file 
Converted all signals to lower case
 2014-12-12 16:34:52 -05:00
aolofsson
94ef357c52 Removing old files not needed by new design 2014-12-12 12:27:22 -05:00
aolofsson
53f1ef0e46 Add register definition for ESYSDEBUG... 2014-12-12 12:20:18 -05:00
aolofsson
88443f7f98 Adding a read only debug register for monitor important elink signals. 
Useful for debugging new hardware.
 2014-12-11 14:51:09 -05:00
Fred Huettig
8a7cae33de Minor fixes for implementation. 2014-11-24 01:57:57 -05:00
Fred Huettig
ad8a088a36 eCfg: Renamed reset input to hw_reset, OR'd into ecfg_reset output. 
eCfg IP updated to match.
 2014-11-19 16:59:04 -05:00
Fred Huettig
1bc118cfcd Merge branch 'elink_redesign' of https://github.com/Parallella/parallella-hw into elink_redesign 
Conflicts:
	fpga/src/ecfg/hdl/ecfg.v
 2014-11-19 12:29:35 -05:00
Fred Huettig
440d932794 New Vivado-friendly modules, testbench for elink gold-vs-new. 2014-11-19 12:02:18 -05:00
aolofsson
6778fce054 Cleaning up old files.. 2014-11-06 15:40:40 -05:00
aolofsson
b151bc90e1 More file organization 
Adding some more utility functions
 2014-11-06 12:19:39 -05:00
aolofsson
60182e52e3 A "complete" elink top level block with all new features added. Still need 
to work on the axi side.
 2014-11-06 12:18:16 -05:00
aolofsson
c01793a902 Adding place holders for hard macros 2014-11-06 12:17:56 -05:00
aolofsson
4819599f00 Fixing interface as 20 bits, fits with Epiphany architecture. 
Very unlikely to EVER change, so hard coding.
 2014-11-06 12:17:09 -05:00
aolofsson
3f513c9d84 Basic interfaces..still need to add the axi signals and fill in the content 2014-11-06 12:16:09 -05:00
aolofsson
d1a669026f Adding readback indicator for slave axi mux 2014-11-06 12:15:19 -05:00
aolofsson
b997ddd691 Adding readback indicator for AXI slave mux 2014-11-06 12:14:49 -05:00
aolofsson
26c5da0cbb Create combined reset (hw+sw) 
Added data select output for axi_slave mux
Signal cleanup (gpio_data)
 2014-11-06 11:52:38 -05:00
aolofsson
0ba677883d Adding run.sh files for simulation 2014-11-05 20:00:57 -05:00
aolofsson
122fb564c8 Changing to 20 bit address interface 2014-11-05 19:59:15 -05:00
aolofsson
536613b230 Changed to 20 bit addressing for clarity in FPGA 2014-11-05 19:49:18 -05:00
aolofsson
2851e01228 Changed to 20 bit address width for clarity in FPGA block 2014-11-05 19:37:25 -05:00
aolofsson
5abdec0b18 Run script for embox 2014-11-05 19:36:58 -05:00
aolofsson
4ab49e07c2 Reorganizing structure to be IP centric 
-Each directory contains one sub block
-Each directory contains a dv/docs/hdl directory, self contained.
-May need to add constraints directory as well at some point.
-This is the right thing to do, make each block modular and self contained.
 2014-11-05 14:31:05 -05:00