FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-30 02:32:53 +08:00
Code Issues Projects Releases Wiki Activity
32 Commits 7 Branches 1 Tag
Commit Graph

5 Commits

Author SHA1 Message Date
aolofsson
7b6b281862 Adding new elink top level file written in verilog. 
Compiles and runs (needs work)
 2014-12-14 22:19:02 -05:00
aolofsson
c9a70e5f6b An unverified clean top level elink design module 2014-12-14 17:25:46 -05:00
aolofsson
94ef357c52 Removing old files not needed by new design 2014-12-12 12:27:22 -05:00
aolofsson
6778fce054 Cleaning up old files.. 2014-11-06 15:40:40 -05:00
aolofsson
60182e52e3 A "complete" elink top level block with all new features added. Still need 
to work on the axi side.
 2014-11-06 12:18:16 -05:00