Andreas Olofsson
7b8460b145
Fixing up issues with database reorg
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- Not sure where the prog_full issue popped up from. (sign of disorganized databsae)
-
2015-11-30 15:07:28 -05:00
Andreas Olofsson
9ddd71024d
Fixing system_bd interface for "mailbox_irq" signal
2015-11-29 12:41:53 -05:00
Andreas Olofsson
038d39def7
Defparam typo
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- Not caught by iverilog!! (file bug??)
- Caught by Vivado.
2015-11-11 14:13:38 -05:00
Andreas Olofsson
0a2ea66b7e
Bug fix. Adding missing ID parameter.
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- would only show up at different ID
- better to always make defauly nonsense
- sneaky...
2015-11-11 13:58:04 -05:00
Andreas Olofsson
61eb56c6f7
Final Vivado fixups:
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- reduced frame fanout, removed clock gater in erx_io (improves speed path)
- driving constants on "wid signals" (proper)
- making lock signal 1 bit wide to remove warning
- moved backed to BUFIO for IDDR blocks
2015-11-09 16:09:12 -05:00
Andreas Olofsson
c84e1c96b7
Adding hdmi pins for parallella
2015-11-09 13:22:08 -05:00
Andreas Olofsson
9383f32764
Making sure ETYPE is set to 0.
2015-11-06 22:41:43 -05:00
Andreas Olofsson
8b3fa77df1
Added missing index
2015-11-06 20:47:16 -05:00
Andreas Olofsson
1fa3543ba1
Changing back to lower cases, works..
2015-11-06 20:46:41 -05:00
Andreas Olofsson
63bf5d25a4
Moving to active low reset
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- Because this is the right thing to do for chips
- Not going to tell you why...
2015-11-06 16:51:57 -05:00
Andreas Olofsson
3969e6d19e
Moving to MIT license
2015-11-06 11:25:05 -05:00
Andreas Olofsson
8b2974feae
Massive reorg!
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- flattening hierarchy
- removing junk
2015-11-06 10:59:22 -05:00
Andreas Olofsson
6cb5f88073
Moving block deisgns into a single Parallella module
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- Easier to maintain
- Better sandbox
2015-11-06 06:56:56 -05:00
