- Creating an arbitrary 'src' directory really doesn't help much...
- Goal is to make each folder self contained
- Make meta repos and individual repos have the same directory structure
- The top level directory was not scaling, too imposing
- Friendlier to download a repo and see a finite number of top level dirs
- We are just getting started...
- Too much junk in there, couldn't understand my own logic 4 weeks later...
- emesh_if is a disaster, I have yet to find a way to write code that lets me remember the pass through bidirectoral logic for more than 1 day. Removed the interface and replaced it with 3 lines of code.
-Mailbox is a pretty useful little block, registers don't belong in the RX space
-Moved registers to the "MESH" group block at bits [10:8].
-Feel good about this, should not change...
-Has been tested to work with test/test_regs.emf
-For new register address, see README.md
cc @olajep @peteasa
- Gating mailbox_not empty with irq_en. bit [28] of RXCFG
- Changing elink output interrupt to "or" of not_empty and full
- Adding mailbox status register (mostly for debug)
- Moving register addresses to make space for mailbox status register
- Fixing wrappers for DV
- Updating README docs with new register map
- Removing mailbox from RX status reg. Doesn't belong there, should be coupled with mailbox for modularity.
- Turns out I had a nasty bug that was masked by using my own RX to loopback the TX. Since the new RX is very benign with a programmable fifo full flag the timing is quite relaxed.
- The legacy elink for e16 has a strict wait policy. When wait is raised high, you must stop pretty much immediately.
- I struggled with testing this bug on the parallella for 2 days.
- Putting together the test environment uncovered the bug in a couple of hours. F**K, I should know better!!
- The axi slave can never drive enough reads to saturate the maxi fifo since it's only sending out one read at a time.
- Changing the system so that a raw elink sits in front of stimulus..
- Turns out there was a bug hidden in the emaxi that can only be found by properly driving a master device with reads. This could not happen in the old environment.
- Note that due to limitations in the esaxi, I had to add the etx_fifo block as an interface (simplest).
- The ESAXI is very limited in that it MUST interface to a fifo with spare entries. (so prog_full). This should be FIXED!
- Minimal test passes, now to try to reproduce the DMA bug..
