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1,594 Commits 7 Branches 1 Tag
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17 Commits

Author SHA1 Message Date
aolofsson
289024fd89 Flattening directory tree (again) 
- Creating an arbitrary 'src' directory really doesn't help much...
- Goal is to make each folder self contained
- Make meta repos and individual repos have the same directory structure
 2022-06-21 14:48:48 -04:00
aolofsson
e89f815b38 Going back to placing all folders in src 
- Only way to scale, final decision!!
 2022-05-29 08:45:00 -04:00
Andreas.Olofsson
d6f5de24d7 Changing hierarchy to promote blocks 2020-01-28 18:12:57 -05:00
Andreas Olofsson
7094173ae9 Reorg! Why? 
- The top level directory was not scaling, too imposing
- Friendlier to download a repo and see a finite number of top level dirs
- We are just getting started...
 2016-03-22 08:13:40 -04:00
Andreas Olofsson
5f16bd672e Changing test extension to "*emf" 
- The last field is a delay argument for stimulus
 2016-01-10 15:55:58 -05:00
Andreas Olofsson
96abfe3105 Initial register test (still debugging) 2015-11-02 19:27:41 -05:00
Andreas Olofsson
34d379ecb9 Adding new "simpler" test infrastruture 
- build elink with one command
- place all tests in tests/ directory
- new stimulus format followed
- dut_elink.v created
 2015-11-02 16:04:46 -05:00
Andreas Olofsson
902ef1b7dd Removing hack on rx clock 2015-09-30 13:00:14 -04:00
Andreas Olofsson
0bfd4d85fc Adding sim parameter 
-lenth of reset pulse should be driven from sim environment
 2015-09-11 18:25:08 -04:00
Andreas Olofsson
e28cd3cb97 Adding search path for include file 2015-07-02 16:47:07 -04:00
Andreas Olofsson
4f487d498e Making simulation more "real" 
-Working with timescale (for viewer mostly)
-Now using TARGET_XILINX as default in sim
 2015-05-06 12:21:39 -04:00
Andreas Olofsson
74fe62e94d Broken testbench connections 2015-04-23 20:04:03 -04:00
Andreas Olofsson
0f0ff55928 Verilator based lint cleanup 2015-04-23 18:57:55 -04:00
Andreas Olofsson
643ceed432 Adding manual test feature to testbench 
-This is as far as I go with fufu testing (random next)
-Add basic test for cleaning up reads/writes
-104 bit packet format for driving transactions, very useful
 2015-04-18 16:14:53 -04:00
Andreas Olofsson
b9d3c5ac5c Verilator lint cleanup 
~10 real bugs
-mostly name mismatches and bit range mistakes
 2015-04-14 14:00:23 -04:00
Andreas Olofsson
73229ff914 Major cleanup, refactoring, and feature completion 
-adding clock bypass mode for esystx[12]
-removing monitor feature on erx
-remove loopback support from doc
-add clock bypass mode for esysclk
-shortening register names (descriptive enough)
-added debug signal information
-moving registers to elink
-making elink version programmable (to support plug in boards)
-reorganized debug signals and added stickys
-added timeout for axi slave
-removed embox status bit (redudant, don't poll status)
-renamed EMBOX0-->EMBOXLO
-moved datain interface straight to ecfg (cleanup)
-changed etx arbiter priority to increase stability
-created the esaxi_mux block
-fixed some missing ports issues in stubs

Now comes the fun part...verification...
Andreas
 2015-04-11 00:04:18 -04:00
aolofsson
0cd5939a26 Adding fofo environment for elink to check for broken signals. 
Too many stub modules to be practical..next need sim models
 2014-12-14 22:17:23 -05:00