12 Commits

Author	SHA1	Message	Date
aolofsson	de63dfd907	Major reorg! ... -stdcells moved to asiclib, doesn't make sense to be vectorized -common is a stupid name, renamed as stdlib	2021-07-29 11:20:44 -04:00
aolofsson	acc72c5762	Removing netlist directory ... -All abstracted information contained in hdl	2021-05-26 14:57:25 -04:00
aolofsson	d0dab83075	Merging rtl and switch models in one verilog file	2021-05-25 19:27:00 -04:00
aolofsson	2eb3e4518b	Prototype for driving cell level parameters	2021-05-25 16:10:50 -04:00
aolofsson	2e8551d468	Adding nor primitive circuit	2021-05-25 13:57:16 -04:00
aolofsson	b2624e803e	Adding switch level modeling of nand gate	2021-05-25 13:48:00 -04:00
aolofsson	3fc3983494	Fixing concatentation errors	2021-05-24 20:56:48 -04:00
aolofsson	9631c50bae	Adding scan cells to standard cell libs	2021-05-24 20:52:04 -04:00
aolofsson	f4184b048a	Adding xor standard cell family	2021-05-24 20:30:20 -04:00
aolofsson	5e151efa51	Adding batch of oa/ao cells	2021-05-24 20:26:05 -04:00
aolofsson	a08ef0d84c	Fixing nset typo	2021-05-24 20:25:55 -04:00
aolofsson	0489dd2d8c	First batch of standard cells	2021-05-24 19:05:20 -04:00