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Author SHA1 Message Date
Andreas Olofsson
81fe46a929 Removing xpr file 
(everything done through tcl)
 2015-11-04 22:12:50 -05:00
Andreas Olofsson
025af1ee54 Yay! Now runs to completion 2015-11-04 22:11:19 -05:00
Andreas Olofsson
ee6a9a93ac Updating scripts 
- adding more compatibility families
 2015-11-04 21:46:15 -05:00
Andreas Olofsson
92272e211d Adding missind dirs in comamnd file 2015-11-04 20:04:44 -05:00
Andreas Olofsson
6a423b5999 Improcing mmcm/pll clock path 
-apparantly the BUFG in the feedback was not liked by the P&R
 2015-11-04 20:02:45 -05:00
Andreas Olofsson
49bf52374d Changing model to use parameter rather than tick-define 2015-11-04 20:01:31 -05:00
Andreas Olofsson
2ed60c5698 Merge branch 'master' of https://github.com/parallella/oh 2015-11-04 19:20:13 -05:00
Andreas Olofsson
3e78d06051 Moving models out of hdl 2015-11-04 19:20:03 -05:00
Andreas Olofsson
dbff2623c1 Cleanup 2015-11-04 19:18:45 -05:00
Andreas Olofsson
96efc91ec1 Filtering more Xilinx junk files 2015-11-04 19:18:11 -05:00
Andreas Olofsson
0cf23a8d1b Reorg 2015-11-04 19:16:50 -05:00
Andreas Olofsson
81b71df54e Reorg 2015-11-04 19:15:05 -05:00
Andreas Olofsson
8938c396b6 Merge pull request #15 from peteasa/packagingPathUpdates 
Updated paths and added missing source
 2015-11-04 17:57:49 -05:00
Andreas Olofsson
e763cc0250 Added filters for all the Xilinx junk 
- git should have only .tcl files really...
 2015-11-04 17:55:01 -05:00
Andreas Olofsson
30077cc1e5 Scripted elink build script (version 0) 
- starting to feel better about structure
 2015-11-04 17:53:54 -05:00
Peter Saunderson
9009113162 Updated paths and added missing source 
Signed-off-by: Peter Saunderson <peteasa@gmail.com>
 2015-11-04 20:14:57 +00:00
Andreas Olofsson
8a8255ddfd Adding common scripts directory 2015-11-04 14:15:49 -05:00
Andreas Olofsson
6b83cdb0d7 Testbench bug fix 
- can't connect a 64 bit interface to a 32bit one...
- (abuse of emaxi..)
 2015-11-03 21:50:26 -05:00
Andreas Olofsson
63e0017275 Stimulus end of test issue 
- Still not 100% on this...but test passes
- Teset was hanging even though  stim_done went high. Ticks not advancing, pointing towards comb loop, but what is different at end of test?
- Now to test read/writes of registers from axi and set the idelay registers
 2015-11-03 19:56:27 -05:00
Andreas Olofsson
6d9d9702d8 Simulation file cleanup 2015-11-03 19:53:43 -05:00
Andreas Olofsson
f849f2410f Adding infrastructure for axi_elink 
- Need to clean up some of these files later
 2015-11-03 19:52:08 -05:00
Andreas Olofsson
36b0f14ca5 "Fixing" wait signal 
- Giving a wait on every ack just doesn't make sense on the read port with a fifo there??
- Makes for a nasty combinatorial loop during integration.
- Test passes (but need to look into this more)
 2015-11-03 19:49:38 -05:00
Andreas Olofsson
6114471935 Adding active signal to interface 
- kind of like "pll lock"
 2015-11-03 19:49:09 -05:00
Andreas Olofsson
3f9ac4d745 Adding missing files 2015-11-03 14:16:50 -05:00
Andreas Olofsson
b4daf73157 Optimizing clock path 
* Sven's help!
* Better to use bufio to keep all paths internal, more determenistic path
 2015-11-03 14:15:09 -05:00
Andreas Olofsson
fb45666b13 Adding idelay config register documentation 2015-11-03 10:46:05 -05:00
Andreas Olofsson
75c9c9deb5 Implemented model for IDELAY 2015-11-03 10:32:56 -05:00
Andreas Olofsson
d7bf1389d6 Changing idelay bit map 
- the 5 bit fields was driving me nuts!
- always work in nibbles, place the msb elsewhere (or work with 16 bit values)
 2015-11-03 10:31:06 -05:00
Andreas Olofsson
275ed5252f Adding test for sweeping idelay and testing reads 
-It works!!!!
 2015-11-03 10:30:20 -05:00
Andreas Olofsson
5d5077b376 Merge branch 'master' of https://github.com/parallella/oh 2015-11-02 20:53:55 -05:00
Andreas Olofsson
46687fe7fd New packet format 
* Removed acess at bit [0], was redundant...
* Frees up one more bit for ctrlmode
 2015-11-02 20:52:27 -05:00
Andreas Olofsson
971b591454 Shifting first byte of packet down by one bit to accomodate new format 
- this of for future proofing
 2015-11-02 20:51:35 -05:00
Andreas Olofsson
02b22a36f3 Fixing test to conform to new stimulus format 2015-11-02 20:51:03 -05:00
Andreas Olofsson
bd16558f73 Merge pull request #11 from olofk/master 
Remove emmu testbench from edma
 2015-11-02 19:37:10 -05:00
Andreas Olofsson
2b67e0007a Updated simulation instructions 2015-11-02 19:28:00 -05:00
Andreas Olofsson
96abfe3105 Initial register test (still debugging) 2015-11-02 19:27:41 -05:00
Andreas Olofsson
a3b0d9b75c Fixing pushback bug 
* Fixed pushback bug at fifo (DUH!)
* Need to verify random pushback at all tx/rx ports
 2015-11-02 16:16:10 -05:00
Andreas Olofsson
ff3af0b21c Fixing include files for emailbox 
- All "folders" should be independent
 2015-11-02 16:15:20 -05:00
Andreas Olofsson
22714f3d9d Adding new emesh format files 
* Adding an improved monitor file
* Adding mesh interface (avoids crud logic at top level)
* A emesh packet memory module
 2015-11-02 16:14:08 -05:00
Andreas Olofsson
983c4db449 Link cleanup 
- Using new packet interface
- Adding active signal, indicating that link is ready. This way you don't need to guess when the link is ready (no magic constants)
- Removed register on por reset input to get rid of x on startup.
 2015-11-02 16:10:05 -05:00
Andreas Olofsson
ec9c3d9e44 Delete old files 2015-11-02 16:08:14 -05:00
Andreas Olofsson
34d379ecb9 Adding new "simpler" test infrastruture 
- build elink with one command
- place all tests in tests/ directory
- new stimulus format followed
- dut_elink.v created
 2015-11-02 16:04:46 -05:00
Andreas Olofsson
af6bebe18a Adding language on licensing 2015-11-01 17:09:12 -05:00
Andreas Olofsson
7f8b95eafd Fixing typos 2015-11-01 16:48:58 -05:00
Andreas Olofsson
97dfc3eeaf Adding descriptions 2015-11-01 16:47:40 -05:00
Andreas Olofsson
62f5490f6b Adding missing file for emailbox 2015-11-01 16:45:39 -05:00
Andreas Olofsson
581c2943f5 Fixing pushback bug in emmu 
- reset was broken!
- need to account for wait
- merging read/write wait for simplicity, otherwise you would need to reset the packets to figure out if it's a read or write transaction...and I don't want to reset every packet throughout the pipe.
 2015-10-19 11:08:28 -04:00
Olof Kindgren
0a2f7ddd5b Remove emmu testbench from edma 
The edma dv directory contained a copy of the emmu testbench instead
of an edma testbench
 2015-10-16 16:04:30 +02:00
Andreas Olofsson
028ba93ea7 Adding more items (work in progress) 2015-10-15 11:00:52 -04:00
Andreas Olofsson
18bccb3442 Adding verilog faq 2015-10-14 23:11:07 -04:00