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63 Commits

Author SHA1 Message Date
aolofsson
289024fd89 Flattening directory tree (again) 
- Creating an arbitrary 'src' directory really doesn't help much...
- Goal is to make each folder self contained
- Make meta repos and individual repos have the same directory structure
 2022-06-21 14:48:48 -04:00
aolofsson
e89f815b38 Going back to placing all folders in src 
- Only way to scale, final decision!!
 2022-05-29 08:45:00 -04:00
Andreas.Olofsson
d6f5de24d7 Changing hierarchy to promote blocks 2020-01-28 18:12:57 -05:00
Andreas Olofsson
7094173ae9 Reorg! Why? 
- The top level directory was not scaling, too imposing
- Friendlier to download a repo and see a finite number of top level dirs
- We are just getting started...
 2016-03-22 08:13:40 -04:00
Andreas Olofsson
e549a63a04 Reorg/cleanup 2016-03-08 19:37:42 -05:00
Andreas Olofsson
844bc13d59 Removing ps7 file 
-Not the right approach..
 2016-02-27 13:37:36 -05:00
Andreas Olofsson
8cb368027c Adding clkdivider model 
-Modeling should be kept separate from real designs
 2016-02-26 19:03:25 -05:00
Andreas Olofsson
3f3728b0bf Removing timescale from file 
-Nasty! Came out of nowhere, I guess compile order changed...
 2016-02-26 19:02:43 -05:00
Andreas Olofsson
4a94d45750 Creating new "CLKDIV" module 
-Model should be separate from design (very different needs)
 2016-02-26 16:56:56 -05:00
Andreas Olofsson
e2e99bd29d Adding read count to fifo interface 
-Also removing valid signal, useless..
 2016-01-20 10:48:04 -05:00
Andreas Olofsson
6e93d0399a Hold hack.. 
-This needs to be resolved! Currently there is a simulation problem with the PLL and IDDR circuit, likely due to the clock divider. Amazingly enough the circuit works in sim and FPGA, but there was some redundant logic hiding this.
-Need to take a closer look at this to get the non-blocking/blocking right in PLL and CLKDIV
 2016-01-19 16:01:15 -05:00
Andreas Olofsson
19fa611bb9 Massive reorganization to impove reuse 
- adding more chip code
- pushing memory stuff into common
- making common "oh_" naming class
-
 2015-11-30 13:45:49 -05:00
Andreas Olofsson
0fc4b6188a Test cleanup 
- added lint script using verilator
- adding verilator filter commands for fifo behavioral
- Longer pushbacks in ememory
 2015-11-28 20:15:06 -05:00
Andreas Olofsson
75cef84075 Timescale stuff 
- Need to look into this again, gotchas here
-
 2015-11-13 16:25:38 -05:00
Andreas Olofsson
24afa3c9a0 Deleting old files 2015-11-12 11:00:23 -05:00
Andreas Olofsson
a44053fbe1 Adding Xilinx behavioral models for fifo 2015-11-12 09:57:55 -05:00
Andreas Olofsson
04cd179f5a Lint fixes for icarus/verilator 2015-11-09 21:57:25 -05:00
Andreas Olofsson
bf614a9873 Cleaning up fifo interface 
- removing redundant signals
- configuring to put synchronizer inside fifo
- one reset only (not two)
 2015-11-09 13:20:46 -05:00
Andreas Olofsson
3969e6d19e Moving to MIT license 2015-11-06 11:25:05 -05:00
Andreas Olofsson
8b2974feae Massive reorg! 
- flattening hierarchy
- removing junk
 2015-11-06 10:59:22 -05:00
Andreas Olofsson
e47fd56a21 Bulk edits (clean up later) 2015-11-06 07:03:28 -05:00
Andreas Olofsson
22a95292d3 Fixing empty models 2015-11-06 07:02:28 -05:00
Andreas Olofsson
81b71df54e Reorg 2015-11-04 19:15:05 -05:00
Andreas Olofsson
6d9d9702d8 Simulation file cleanup 2015-11-03 19:53:43 -05:00
Andreas Olofsson
75c9c9deb5 Implemented model for IDELAY 2015-11-03 10:32:56 -05:00
Andreas Olofsson
c60f9236da Adding hack model for RDY signal 
-should probably last for more cycles thatn this?
 2015-10-07 19:18:54 -04:00
Andreas Olofsson
0a73ff3fc5 Adding dynamic tap value behavior 2015-10-07 19:18:27 -04:00
Andreas Olofsson
8c9fea0362 Adding async reset behavior 2015-10-07 19:17:59 -04:00
Andreas Olofsson
13bee36d88 Fixing reset behavioral bug 2015-10-07 19:17:35 -04:00
Andreas Olofsson
a39966d9f1 Adding IP for fifo 2015-10-07 12:04:50 -04:00
Andreas Olofsson
ad41b25e42 Making reset async 2015-10-07 12:04:15 -04:00
Andreas Olofsson
8311e4a04e dummy 2015-10-07 11:58:35 -04:00
Andreas Olofsson
790480bedd Adding dummy cells 2015-10-07 11:57:52 -04:00
Andreas Olofsson
394920a1e7 Addding phase delay tracking 
- As a dirty a model hack as they come, using positive and negative edge of CLKIN to sample the signal and phase align the clock output.
- Will only work with div 2/4/8 etc
- There may be other issues, have to think about it...
- But the test now passes cleanly and the clocks look good.
 2015-09-30 13:40:11 -04:00
Andreas Olofsson
cada5bd9b6 Adding clock tracking on PLL/DLL 
-Fixed PLL model to make it properly phase aligned with CLKIN
 2015-09-14 20:23:25 -04:00
Andreas Olofsson
c627827a6b Fifo cleanup 
-Adding model (one source..)
-generate for 104x32 for xilinx
-making prog_full the default full indicator
-bringing out almost_full for future use
-fixing interface change in all modules
 2015-07-02 16:59:38 -04:00
Andreas Olofsson
0c66100d6d Adding half full signal to fifo 2015-07-02 15:00:18 -04:00
Andreas Olofsson
51a642a7b7 Adding 32 deep interface fifo for AXI 
-needed to support burst properly
 2015-07-02 14:59:57 -04:00
Patrik Lindström
4a749bf2d8 timing fixes 2015-07-01 00:14:46 +02:00
Andreas Olofsson
b0c7b75407 Adding OBUF model 2015-06-25 15:42:20 -04:00
Andreas Olofsson
7b8a9cf474 Adding IP file for async fifo 
-This is the place for all generic IP blocks
 2015-05-23 22:24:44 -04:00
Andreas Olofsson
1ec8991e2a Adding IDELAY elements to xilibs 2015-05-16 22:07:17 -04:00
Andreas Olofsson
cd624d6531 Adding IDDR model 2015-05-15 15:27:45 -04:00
Andreas Olofsson
1f89e682bb Adding warning regarding clock divider 
-For now only div by 2/4/8 supported
-Really need to implement general purpose integer clock divider!
 2015-05-15 15:26:59 -04:00
Andreas Olofsson
ee363f6119 Fixed ODDR model for SAME_EDGE mode 2015-05-15 09:46:08 -04:00
Andreas Olofsson
836c4a65a8 Adding PLLE2_ADV model 2015-05-14 22:49:42 -04:00
Andreas Olofsson
a2d8c5c453 Adding PLL LOCK functionality 
-not accurate, but at least it gives some dunmy behavior for PLLLOCK
 2015-05-14 22:48:55 -04:00
Andreas Olofsson
58aeb0ee87 Adding warning message to ISERDES/OSERDES 
-Don't use them!!
 2015-05-13 23:33:26 -04:00
Andreas Olofsson
ade946ce90 Updating with new (and correct) modeling 2015-05-13 23:31:52 -04:00
Andreas Olofsson
dc8cb83268 Cleanup 2015-05-07 23:49:50 -04:00