FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-17 20:02:53 +08:00
Code Issues Projects Releases Wiki Activity
724 Commits 7 Branches 1 Tag
Commit Graph

724 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Andreas Olofsson
4477f55cf5 Separating clocks for tx/rx 
- more modular, understandable, reusable
 2015-10-07 19:08:32 -04:00
Andreas Olofsson
947a804c62 Making reset async 
- making ecfg_elink reset only depend on por (otherwise chicken and egg)
-
 2015-10-07 14:46:12 -04:00
Andreas Olofsson
634b1f81f0 Making reset async 2015-10-07 12:06:30 -04:00
Andreas Olofsson
a39966d9f1 Adding IP for fifo 2015-10-07 12:04:50 -04:00
Andreas Olofsson
ad41b25e42 Making reset async 2015-10-07 12:04:15 -04:00
Andreas Olofsson
8311e4a04e dummy 2015-10-07 11:58:35 -04:00
Andreas Olofsson
790480bedd Adding dummy cells 2015-10-07 11:57:52 -04:00
Andreas Olofsson
d7d959da45 Adding software programmable IDELAY 
- This is DEFINITELY the way to do things, sweep the delays and find the right value. No f'ing way to get these stupid FPGAs to work otherwise with the ridiculuosly over margined PVT nubmers they are running through the STAs. I understand they want to make the design bullet proof, but as a result designers are wasting countless hours overoptimzinng designs and being clever. So much performance is left on the table for expert users.
- Lesson: I/O design should be "self syncrhonizing". Only contraints in the design should be create_clk
- Made RX clock async, too tricky to guarantee that there clock is there.  No way to do this if the clock sources are actually independent for RX/TX!
 2015-10-07 11:49:46 -04:00
Andreas Olofsson
8bba86d6cd Adding static phase shif ton RXCLK 
-this becomes irrelavent once we have the dynamic idelay on input
 2015-10-07 08:57:50 -04:00
Andreas Olofsson
394920a1e7 Addding phase delay tracking 
- As a dirty a model hack as they come, using positive and negative edge of CLKIN to sample the signal and phase align the clock output.
- Will only work with div 2/4/8 etc
- There may be other issues, have to think about it...
- But the test now passes cleanly and the clocks look good.
 2015-09-30 13:40:11 -04:00
Andreas Olofsson
6428f5ee46 Driving clocks from MMCM instead of from BUFIO 2015-09-30 13:00:45 -04:00
Andreas Olofsson
902ef1b7dd Removing hack on rx clock 2015-09-30 13:00:14 -04:00
Andreas Olofsson
eaea05d0cd Fixed pll clocking bug 
-apparantly the MMCM needs a reset after the clock changes
-need to hold reset high until we know that there is an active clock on input
-doesn't it make more sense to use idelay?
 2015-09-27 08:41:24 -04:00
Andreas Olofsson
415b8113df Adding proper "ETYPE" for wait signals 
-single and diff should be fully supported
 2015-09-27 08:40:36 -04:00
Andreas Olofsson
8c4c730682 added etype to elink instantiation 2015-09-27 08:40:09 -04:00
Andreas Olofsson
531a1fc85a fixing cut off line 2015-09-25 15:42:22 -04:00
Andreas Olofsson
90bd596edc Merge branch 'master' of https://github.com/parallella/oh 2015-09-25 15:41:19 -04:00
Andreas Olofsson
36f9764b07 Linking in clocking diagram 2015-09-25 15:40:52 -04:00
Andreas Olofsson
b0cc7bf006 shrinking diagram even more... 2015-09-25 15:39:26 -04:00
Andreas Olofsson
e965023273 shrinking diagram 2015-09-25 15:36:37 -04:00
Andreas Olofsson
fffac5e4b6 adding clocking png file 2015-09-25 15:25:33 -04:00
Andreas Olofsson
e42443574d Adding clocking diagram 2015-09-25 15:22:12 -04:00
Andreas Olofsson
8b9ddb5d34 Hard coding for ephycard, may need to fix back later... 2015-09-25 15:21:21 -04:00
Andreas Olofsson
22a2443d1e Removed rendundant clock 2015-09-25 15:20:21 -04:00
Andreas Olofsson
cfbbfeb574 Adding "ETYPE" as a parameter 
-set to 0 for parallella
-set to 1 for ephycard
 2015-09-14 22:03:22 -04:00
Andreas Olofsson
58226bc867 Returned erx_io to old format! 
-Burst works again!
-There was definitely a bug on the frame signal, need to pay close attention to all the clock signals, let's review!
 2015-09-14 22:02:16 -04:00
Andreas Olofsson
d7508f9938 DV cleanup 
-Set VCO_MULT to 1 for PLL. Dirty hack to allow the RX clk to phase align with the input. Otherwise, if you multiply the VCO clock and then divide, you get a random phase alignment the way the current clock divider is written.
-Changed the fifo_cdc to 32 entries. Forgot that I had changed the fifo_cdc to hard coded per number of entries. Really need to have a parametrixed model that works!!
 2015-09-14 21:58:52 -04:00
Andreas Olofsson
0415b01753 Clock changes 
-separated PLL and MMCM
-rx clock only on PLL
-removed lock (fix further)
-simplified parameters, more intuitive to change
 2015-09-14 20:25:12 -04:00
Andreas Olofsson
cada5bd9b6 Adding clock tracking on PLL/DLL 
-Fixed PLL model to make it properly phase aligned with CLKIN
 2015-09-14 20:23:25 -04:00
Andreas Olofsson
31f6c94857 Removing random wait for now: 
-the read-after write is annoying
 2015-09-14 20:22:18 -04:00
Andreas Olofsson
31bbb6476b Remving delay from mmu 2015-09-14 13:29:42 -04:00
Andreas Olofsson
23e0f60388 cleanup 2015-09-14 13:28:44 -04:00
Andreas Olofsson
0bfd4d85fc Adding sim parameter 
-lenth of reset pulse should be driven from sim environment
 2015-09-11 18:25:08 -04:00
Andreas Olofsson
c00003e9a3 Changing clocks back: 
-txclk should depend on the sysclk not rxclk
 2015-09-11 18:24:00 -04:00
Andreas Olofsson
090a6c2b1e Fixing interfaces due to moving idelay ctrl to clock block 2015-09-11 12:15:22 -04:00
Andreas Olofsson
52cded4eb2 Fixing Icarus compile error 
-multi dimensional parameters not working
-trying with regs
 2015-09-11 12:08:46 -04:00
Andreas Olofsson
0ec0794bbd Filling in missing parameters 
-needed for Icarus verilog simulator
 2015-09-11 12:08:07 -04:00
Andreas Olofsson
b4fa198ed7 Merge pull request #10 from olajep/patch-1 
README.md: ETX_CFG == 0xF0210
 2015-09-07 15:42:00 -04:00
Ola Jeppsson
efb1eea253 README.md: ETX_CFG == 0xF0210 2015-09-07 19:50:28 +02:00
Andreas Olofsson
012b08a1b6 Merge pull request #9 from plindstroem/master 
Changing receiver clock
 2015-09-01 10:34:01 -04:00
Patrik Lindström
137d8bfdb0 Changing receiver clock 
Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>
 2015-09-01 16:11:52 +02:00
Andreas Olofsson
f753325686 Merge pull request #8 from plindstroem/master 
Receiver fixes
 2015-08-31 10:12:38 -04:00
Patrik Lindström
14beca6a8f Script fixes 
Signed-off-by: Patrik Lindström <patrik.lindstrom@foi.se>
 2015-08-25 18:21:19 +02:00
Patrik Lindström
8f144a050a Script fixes 
Signed-off-by: Patrik Lindström <patrik.lindstrom@foi.se>
 2015-08-25 18:17:30 +02:00
Patrik Lindström
abebbeb7dd Adding xgui 
Signed-off-by: Patrik Lindström <patrik.lindstrom@foi.se>
 2015-08-25 14:58:37 +02:00
Patrik Lindström
a5c160fc0d Script fixes 
Signed-off-by: Patrik Lindström <patrik.lindstrom@foi.se>
 2015-08-25 13:03:44 +02:00
Patrik Lindström
1a642a31d6 Removing ephycard define 
Signed-off-by: Patrik Lindström <patrik.lindstrom@foi.se>
 2015-08-25 12:40:48 +02:00
Patrik Lindström
e598635815 Script fixes 
Signed-off-by: Patrik Lindström <patrik.lindstrom@foi.se>
 2015-08-25 12:36:23 +02:00
Patrik Lindström
5e8b10eafb Bug fixes 
Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>
 2015-08-24 22:50:28 +02:00
Patrik Lindström
98a17d6ccf Changing RX clocking 
Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>
 2015-08-24 22:39:51 +02:00